Semiconductor memory device and semiconductor package

1. A semiconductor memory, comprising:

a memory unit including a first memory sub region having a first memory cell and a second memory sub region having a second memory cell;

a temperature information provider to provide temperature information;

a temperature estimator to estimate a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information, the temperature estimator to estimate the first and second temperatures based on predetermined relationship information indicative of a relationship between the temperature information and the first and second temperatures;

a first sub region controller to control the first memory sub region based on the first temperature, the first sub region controller is to refresh the first memory cell during a first refresh period corresponding to the first temperature; and

a second sub region controller to control the second memory sub region based on the second temperature, the second sub region controller is to refresh the second memory cell during a second refresh period corresponding to the second temperature, wherein:

the first memory sub region has m number of refresh addresses;

the second memory sub region has n number of refresh addresses, where m and n are natural numbers greater than 1;

the first sub region controller includes:

a first oscillator to generate a first pulse signal including m number of pulses during the first refresh period in correspondence to the first temperature,

a first address counter to generate a first refresh address indicating a refresh address of the first memory sub region where a refresh operation is to be performed in response to the first pulse signal, and

a first refresh circuit to refresh memory cells corresponding to the first refresh address in response to the first pulse signal; and

the second sub region controller includes:

a second oscillator to generate a second pulse signal including n number of pulses during the second refresh period in correspondence to the second temperature,

a second address counter to generate a second refresh address indicating a refresh address of the second memory sub region where the refresh operation is to be performed in response to the second pulse signal, and

a second refresh circuit to refresh memory cells corresponding to the second refresh address in response to the second pulse signal.

2. A semiconductor memory, comprising:

a memory unit including a first memory sub region having a first memory cell and a second memory sub region having a second memory cell;

a temperature information provider to provide temperature information;

a temperature estimator to estimate a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information, the temperature estimator to estimate the first and second temperatures based on predetermined relationship information indicative of a relationship between the temperature information and the first and second temperatures;

a first sub region controller to control the first memory sub region based on the first temperature, the first sub region controller is to refresh the first memory cell during a first refresh period corresponding to the first temperature; and

a second sub region controller to control the second memory sub region based on the second temperature, the second sub region controller is to refresh the second memory cell during a second refresh period corresponding to the second temperature, wherein:

the first memory sub region has m number of refresh addresses;

the second memory sub region has n number of refresh addresses, where m and n are natural numbers greater than 1;

the first sub region controller includes:

a first pulse signal generation circuit to receive a third pulse signal and to generate a first pulse signal having m number of pulses during the first refresh period from the third pulse signal,

a first address counter to generate a first refresh address indicating a refresh address of the first memory sub region where a refresh operation is to be performed in response to the first pulse signal, and

a first refresh circuit to refresh memory cells corresponding to the first refresh address in response to the first pulse signal; and

the second sub region controller includes:

a second pulse signal generation circuit to receive the third pulse signal and to generate a second pulse signal having n number of pulses during the second refresh period from the third pulse signal,

a second address counter to generate a second refresh address indicating a refresh address of the second memory sub region at which the refresh operation is to be performed in response to the second pulse signal, and

a second refresh circuit to refresh memory cells corresponding to the second refresh address in response to the second pulse signal.

3. The device as claimed in claim 2 , wherein the first pulse signal generation circuit and the second pulse signal generation circuit respectively include a first skip circuit and a second skip circuit that partially or wholly pass pulses of the third pulse signal.

4. The device as claimed in claim 3 , wherein a pulse frequency of the third pulse signal is equal to or higher than a higher of a pulse frequency of the first pulse signal and a pulse frequency of the second pulse signal.

5. The device as claimed in claim 2 , further comprising:

an internal oscillator to generate the third pulse signal.

6. The device as claimed in claim 2 , wherein the third pulse signal is generated in response to a refresh command received from an external device.