Semiconductor chip and stacked type semiconductor package having the same
The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.
1. A semiconductor chip, comprising:
a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, the first surface being a bottom surface of the semiconductor chip body, and the second surface being a top surface of the semiconductor chip body;
a plurality of first and second through electrodes passing through the semiconductor chip body such that bottom surfaces of the first and second through electrodes are electrically connected to the bonding pads;
an insulating layer formed over the second surface of the semiconductor chip body such that top surfaces of the first and second through electrodes are not covered by the insulating layer; and
a first heat spreading layer formed over a top surface of the insulating layer,
wherein the top surface of the insulating layer is coplanar with the top surfaces of the first and second through electrodes.
2. The semiconductor chip of claim 1 , wherein the first heat spreading layer comprises a thickness of 0.3 to 6 μm and a thermal conductivity of 500 to 5000 watts per meter kelvin (W/mK).
3. The semiconductor chip of claim 2 , wherein the first heat spreading layer is formed of graphene.
4. The semiconductor chip of claim 1 , wherein the first heat spreading layer is formed such that the first heat spreading layer is in direct contact with the first through electrodes but is not in contact with the second through electrodes.
5. The semiconductor chip of claim 4 , wherein the first heat spreading layer is formed such that the first heat spreading layer covers the first through electrodes.
6. The semiconductor chip of claim 4 , wherein the first through electrodes are power electrodes or ground electrodes, and the second through electrodes are signal electrodes.
7. The semiconductor chip of claim 4 , further comprising:
a plurality of third through electrodes formed within the semiconductor chip body, electrically connected to the bonding pads at one ends of the third through electrodes and having a potential different from the first through electrodes; and
a second heat spreading layer formed over the insulating layer such that the second heat spreading layer is in direct contact with the third through electrodes.
8. The semiconductor chip of claim 1 , wherein the first heat spreading layer is formed such that it is not in direct contact with the first and second through electrodes.
9. The semiconductor chip of claim 8 , wherein the first heat spreading layer is formed such that the ends thereof, adjacent to the first and second through electrodes, are placed 5 μm to 100 μm from the first and second through electrodes.
10. The semiconductor chip of claim 1 , further comprising:
first connection electrodes formed over the respective bonding pads; and
second connection electrodes formed over the respective other ends of the first and second through electrodes.