Semiconductor package including stacked chips and method of fabricating the same
A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and a block selection circuit configured to, connect the redundancy blocks of the first and second slave chips, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.
1. A semiconductor package comprising:
first and second slave chips stacked vertically; and
a master chip connected to the first and second slave chips,
each of the first and second slave chips including,
a plurality of memory blocks, the memory blocks arranged along first and second directions perpendicular to each other, and
a redundancy block, the redundancy block disposed between the memory blocks which are adjacent to each other in the first direction and between the memory blocks which are adjacent to each other in the second direction, and
the master chip including,
a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and
a block selection circuit configured to connect the redundancy block of the first slave chip, the redundancy block of the second slave chip, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.
2. The semiconductor package of claim 1 , wherein the fuse block comprises:
a first fuse box configured to output a first fuse signal including information indicating an address of the defective memory block of the first slave chip; and
a second fuse box configured to output a second fuse signal including information indicating an address of the defective memory block of the second slave chip.
3. The semiconductor package of claim 2 , wherein the block selection circuit comprises:
a first block selection unit configured to connect the redundancy block of the first slave chip and the one or more non-defective memory blocks of the first slave chip to the input/output circuit in response to the first fuse signal; and
a second block selection unit configured to connect the redundancy block of the second slave chip and the one or more non-defective memory blocks of the second slave chip to the input/output circuit in response to the second fuse signal.
4. The semiconductor package of claim 1 , wherein the fuse block is configured to cut off power supply to the defective memory blocks of each of the first and second memory blocks, respectively.
5. The semiconductor package of claim 1 , wherein the block selection circuit is connected to input/output lines of the plurality of memory blocks and the redundancy block of the first and second slave chips via one or more through silicon vias.
6. The semiconductor package of claim 1 , wherein a first block from among the one or more non-defective memory blocks of the second slave chip is stacked on the defective memory block of the first slave chip, so that the first memory block of the second slave chip is connected to the defective memory block of the first slave chip.
7. The semiconductor package of claim 1 , wherein the plurality of memory blocks and the redundant memory blocks of the first slave chip are electrically separated from each other, and the plurality of memory blocks and the redundant memory blocks of the second slave chip are electrically separated from each other.
8. A semiconductor package comprising:
a plurality of slave chips stacked vertically, each of the plurality of slave chips including,
a plurality of first memory units, each of the first memory unit including first through silicon vias, and
a redundancy memory unit including second through silicon vias; and
a master chip connected to the plurality of slave chips via the first and the second through silicon vias, the master chip including a fuse unit configured to repair a defective memory unit detected from each of the plurality of slave chips by using the redundancy unit of each of the plurality of slave chips,
wherein the memory units are arranged along first and second directions perpendicular to each other, and
the redundancy unit is disposed between the memory units which are adjacent to each other in the first direction and between the memory units which are adjacent to each other in the second direction.