IP Library › Granted Patent US 9,431,128
Granted Patent B2
US 9,431,128 · App. 14/635,894 · Granted Aug 30, 2016

Semiconductor device including fuse circuit

Inventors: Yusuke Sakamoto (Tokyo, JP); Kenji Yoshida (Tokyo, JP)
Assignee: Micron Technology, Inc.
G11C17/16G11C17/18G11C29/789H03K19/17768
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Quick Facts
Patent No.
US 9,431,128
App. No.
14/635,894
Granted
Aug 30, 2016
Kind
B2
Abstract

Disclosed herein is an apparatus that includes a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element, and a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal, the third voltage different from the second voltage.

Claims (43)

1. An apparatus comprising:

a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element; and

a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal, the third voltage different from the second voltage,

wherein a difference in voltage between the first and third voltages is less than a difference in voltage between the first and second voltages.

2. An apparatus comprising:

a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage, or a second voltage responsive to a state of the fuse element; and

a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal, the third voltage different from the second voltage,

wherein the second voltage is greater in absolute value than the third voltage.

3. The apparatus of claim 2 , wherein the first voltage is greater in potential than each of the second and third voltages.

4. An apparatus comprising:

a fuse circuit including a fuse element the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element; and

a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal, the third voltage different from the second voltage,

wherein the fuse circuit is configured to be supplied with the first voltage during a first period of time and change its voltage to the second voltage responsive to the state of the fuse element during, a second period of time following the first period of time, and

wherein the fuse circuit is configured to change its voltage to the second voltage during the second period of time on condition that the fuse element is programmed.

5. The apparatus of claim 4 , wherein the fuse circuit is configured to maintain its voltage at the first voltage during the second period of time on condition that the fuse element not programmed.

6. An apparatus comprising:

a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element;

a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal the third voltage different from the second voltage; and

a P conductivity type transistor comprising a gate supplied with the third voltage and a channel between the sense circuit and the fuse circuit.

7. An apparatus comprising:

a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element;

a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first out signa 1 , the third voltage different from the second voltage; and

an N conductivity type transistor comprising a gate supplied with the third voltage and a channel between the sense circuit and the fuse circuit.

8. An apparatus comprising:

a pumping circuit configured to be supplied with a first voltage and a second voltage and perform a pumping operation based on the first voltage and the second voltage to generate a third voltage at an output node;

a sense circuit; and

an electrical fuse including a first node coupled to the output node of the pumping circuit and a second node coupled to the sense circuit;

wherein the pumping circuit is further configured to supply the third voltage to the first node of the electrical fuse when the sense circuit amplifies a voltage at the second node of the electrical fuse.

9. The apparatus of claim 8 , wherein the third voltage is a negative voltage.

10. The apparatus of claim 8 , further comprising:

an additional pumping circuit configured to be supplied with the first voltage and the second voltage and perform an additional pumping operation based on the first voltage and the second voltage to generate a fourth voltage at an additional output node; and

a connecting circuit coupled between the additional output node and the second node of the electrical fuse, the connecting circuit configured to supply the fourth voltage to the second node of the electrical fuse when the connecting circuit is enabled.

11. The apparatus of claim 10 , wherein the additional pumping circuit is configured to stop the additional pumping operation when the sense circuit amplifies the voltage at the second node of the electrical fuse.

12. The apparatus of claim 8 , further comprising a P conductivity type transistor coupled between the sense circuit and the second node of the electrical fuse, the P conductivity type transistor having a gate supplied with the second voltage.

13. The apparatus of claim 8 , further comprising an N conductivity type transistor coupled between the sense circuit and the second node of the electrical fuse, the N conductivity type transistor having a gate supplied with the second voltage.

14. An apparatus comprising:

a fuse circuit including a fuse element;

a sense circuit;

a first transistor coupled between a first node of the fuse circuit and an input node of the sense circuit, the first transistor having a gate supplied with a constant voltage; and

a second transistor coupled in series to the first transistor between the first node of the fuse circuit and the input node of the sense circuit, wherein the second transistor is configured to turn on during a first mode and turn off during a second mode.

15. The apparatus of claim 14 , wherein the fuse circuit further includes a second node, the first node is supplied with a first voltage and the second node is supplied with a second voltage during the first mode, the first voltage is greater in potential than the second voltage.

16. The apparatus of claim 15 , wherein the constant voltage is different from the second voltage.

17. The apparatus of claim 16 , wherein the first node is supplied with a third voltage and the second node is supplied with the second voltage during the second mode.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2015
From: SAKAMOTO, YUSUKE; YOSHIDA, KENJI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 035069/0784 →
Priority Claims (1)
JP 2014-041562 · Mar 4, 2014 · national
Continuity (1)
Related Publication 20150255169A1 · Sep 10, 2015