Methods for forming interconnections between top electrodes in memory cells by a two-step chemical-mechanical polishing (CMP) process
Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material.
1. A method for forming an array of memory cells, comprising:
forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode;
forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures;
etching-back the interconnection conductive material;
forming a dielectric material over the interconnection conductive material after etching-back and over a reference level adjacent the plurality of vertical structures;
chemical mechanical polishing (CMPing) the dielectric material to remove a first portion of the dielectric material from over the interconnection conductive material while keeping a second portion of the dielectric material over the reference level; and
forming a conductive line over the interconnection conductive material after etching-back the interconnection conductive material.
2. The method of claim 1 , wherein forming the interconnection conductive material includes forming the interconnection conductive material from a same material as the respective top electrodes of the plurality of vertical structures.
3. The method of claim 1 , further comprising:
forming the interconnection conductive material includes forming the interconnection conductive material over the respective top electrodes of the plurality of vertical structures; and
wherein etching back the interconnection conductive material includes removing portions of the interconnection conductive material without exposing the respective top electrodes of the plurality of vertical structures.
4. The method of claim 1 , further comprising forming a conductive material over the interconnection conductive material,
wherein etching-back the interconnection conductive material includes etching-back the conductive material formed over the interconnection conductive material.
5. The method of claim 4 , wherein etching-back the interconnection conductive material includes removing the conductive material to reach portions of the interconnection conductive material.
6. The method of claim 5 , wherein etching-back the conductive material includes removing all of the conductive material over the interconnection conductive material.
7. The method of claim 5 , wherein etching-back the conductive material includes:
removing conductive material over first portions of the interconnection conductive material; and
not removing conductive material over second portions of the interconnection conductive material.
8. The method of claim 1 , further comprising:
sealing the vertical structures with a dielectric material formed between and over the plurality of vertical structures; and
etching the dielectric material to expose the respective top electrodes of the plurality of vertical structures before forming the interconnection conductive material.
9. The method of claim 8 , wherein forming the plurality of vertical structures includes removing all of a hard mask over the top electrode before sealing the vertical structures with the dielectric material.
10. The method of claim 8 , wherein etching the dielectric material to expose the respective top electrodes of the plurality of vertical structures includes etching the formed dielectric material to expose up to one half of a thickness of the respective top electrodes of the plurality of vertical structures.
11. The method of claim 10 , wherein forming the plurality of vertical structures each having the top electrode includes forming each top electrode of the plurality of vertical structures to have a sufficient thickness such that up to one half of a thickness of the respective top electrodes of the plurality of vertical structures can be exposed without exposing the memory element or switch element underlying the top electrode.
12. The method of claim 1 , wherein the reference level is a substrate, and wherein forming the plurality of vertical structures includes forming the plurality of vertical structures over the substrate.
13. The method of claim 1 , wherein controlling termination of CMPing the dielectric material at least partially responsive to detecting the interconnection conductive material.
14. The method of claim 1 , further comprising:
forming a chop mask over a first portion of the plurality of vertical structures and not over a second portion of the plurality of vertical structures;
performing a chop etch of the second portion of the plurality of vertical structures,
wherein forming the dielectric material over the interconnection conductive material and over the reference level adjacent the plurality of vertical structures includes forming the dielectric material over the first and second portions of the plurality of vertical structures, the reference level being located adjacent second portion of the plurality of vertical structures.
15. The method of claim 14 , wherein forming the interconnection conductive material between the respective top electrodes of the plurality of vertical structures includes forming a uniform thickness of the interconnection conductive material over the vertical structures and over the reference level adjacent the plurality of vertical structures; and
wherein CMPing the dielectric material includes CMPing the interconnection conductive material.
16. An array of memory cells formed according to the method of claim 1 .
17. A method for forming an array of memory cells, comprising:
forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode;
sealing the vertical structures with dielectric material formed between and over the plurality of vertical structures;
forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures;
etching-back the interconnection conductive material;
forming a conductive material over the interconnection conductive material;
etching-back the conductive material; and
forming a conductive line over the interconnection conductive material after etching-back the conductive material;
wherein etching-back the interconnection conductive material includes etching-back the dielectric material to a lower elevation than adjacent vertical structures so as to expose the respective top electrodes of the plurality of vertical structures before forming the interconnection conductive material.
18. The method of claim 17 , wherein etching-back the conductive material includes removing all of the conductive material.
19. The method of claim 17 , wherein forming a plurality of vertical structures includes removing all of a hard mask over the top electrode before sealing the vertical structures with the dielectric material.
20. The method of claim 17 , wherein etching the dielectric material to expose the respective top electrodes of the plurality of vertical structures includes etching the dielectric material to expose up to one half of a thickness of the respective top electrodes of the plurality of vertical structures.
21. The method of claim 17 , wherein forming the plurality of vertical structures each having the top electrode includes forming each top electrode of the plurality of vertical structures to have a sufficient thickness such that up to one half of a thickness of the respective top electrodes of the plurality of vertical structures can be exposed without exposing the memory element or switch element underlying the top electrode.
22. The method of claim 17 , further comprising:
forming a second dielectric material over the interconnection conductive material and over a reference level adjacent the plurality of vertical structures; and
chemical mechanical polishing (CMPing) the second dielectric material to remove the second dielectric material from over the interconnection conductive material.
23. The method of claim 22 , wherein forming the plurality of vertical structures includes forming the plurality of vertical structures over the reference level, and wherein the reference level is a substrate.
24. An array of memory cells formed according to the method of claim 17 .
25. A method for forming an array of memory cells, comprising:
forming a stack of materials over a substrate that includes a material corresponding to a top electrode over a material corresponding to a memory element over a material corresponding to a middle electrode over a material corresponding to a switch element over a material corresponding to a bottom electrode over a material corresponding to a first conductive line;
patterning a hard mask over the stack of materials;
etching the stack of materials into vertical structures according to the patterned hard mask;
forming a first dielectric material over the vertical structures;
dry etching the first dielectric material to expose up to one half of the top electrode of each of the vertical structures and until a portion of the substrate not between the vertical structures is exposed;
forming interconnecting conductive material between and over the top electrode of each of the vertical structures and over the exposed portion of the substrate not between the vertical structures; and
dry etching the interconnecting conductive material until the portion of the substrate not between the vertical structures is re-exposed,
wherein etching the stack of materials include removing the hard mask from the vertical structures.
26. The method of claim 25 , further comprising:
forming a second dielectric material over the dry-etched interconnecting conductive material;
removing a portion of the second dielectric material to expose the dry-etched interconnecting conductive material;
forming a conductive material over the exposed dry-etched interconnecting conductive material; and
removing the conductive material formed over the interconnecting conductive material such that the conductive material remains on first portions of the interconnecting conductive material and the conductive material is removed from second portions of the interconnecting conductive material by chemical-mechanical polishing techniques; and
forming material corresponding to a second conductive line over the conductive material and the interconnecting conductive material.
27. An array of memory cells formed according to the method of claim 26 .