Field effect transistor constructions and memory arrays

1. A field effect transistor construction comprising:

a stack comprising, in ascending order, a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region; the stack having a sidewall; the sidewall having a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region;

third insulative material along an entirety of the middle portion of the sidewall;

a channel region material along the third insulative material and spaced from the conductive gate by the third insulative material; the channel region material being directly against at least part of the bottom portion of the sidewall, and being directly against at least part of the top portion of the sidewall; and

the channel region material comprising transition metal chalcogenide.

2. The construction of claim 1 wherein the channel region material comprises transition metal dichalcogenide and/or transition metal trichalcogenide.

3. The construction of claim 1 wherein the channel region material comprises one or more chalcogenides selected from the group consisting of molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, indium sulfide and indium selenide.

4. The construction of claim 1 wherein the channel region material extends only partially along one or both of the top and bottom portions of the sidewall.

5. The construction of claim 1 wherein the channel region material extends entirely along at least one of the top and bottom portions of the sidewall.

6. The construction of claim 1 wherein the channel region material extends entirely along both of the top and bottom portions of the sidewall.

7. The construction of claim 1 wherein the third insulative material extends along the first insulative material.

8. The construction of claim 1 wherein the third insulative material extends along the second insulative material.

9. A field effect transistor construction comprising:

a bottom source/drain region supported by an insulative base;

a conductive gate directly above the bottom source/drain region;

a top source/drain region directly above the conductive gate;

insulative material along a sidewall of the conductive gate;

channel region material along the insulative material and spaced from the conductive gate by the insulative material; the channel region material extending at least partially along a sidewall of the bottom source/drain region and at least partially along a sidewall of the top source/drain region; and

the channel region material having a thickness of from 1 monolayer to 7 monolayers and comprising transition metal chalcogenide.

10. The construction of claim 9 wherein the channel region material comprises transition metal dichalcogenide and/or transition metal trichalcogenide.

11. The construction of claim 9 wherein the channel region material comprises one or more chalcogenides selected from the group consisting of molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, indium sulfide and indium selenide.

12. The construction of claim 9 having mirror symmetry along a vertical plane such that the channel region material and insulative material are along two opposing sides of the construction.

13. The construction of claim 9 not having mirror symmetry along a vertical plane.

14. The construction of claim 9 wherein the channel region material extends entirely along the sidewall of the bottom source/drain region.

15. The construction of claim 9 wherein the channel region material extends entirely along the sidewall of the top source/drain region.

16. The construction of claim 9 wherein the channel region material extends entirely along the sidewalls of the top and bottom source/drain regions.

17. A method of forming transistors, comprising:

forming a stack comprising, an ascending order, first source/drain region material, first insulative material, gate material, second insulative material and second source/drain material;

patterning the first insulative material, gate material, second insulative material and second source/drain material into pillars;

forming gate dielectric material along sidewalls of the pillars, the gate dielectric material being along the gate material and not along the second source/drain material;

utilizing the pillars as a mask during an etch through the drain region material;

the etch forming the drain region material into pedestals beneath the pillars;

forming channel region material along sidewalls of the pillars and pedestals, and leaving gaps over regions between the pillars and pedestals, the channel region material having a thickness of from 1 monolayer to 7 monolayers; and

filling the gaps with third insulative material and planarizing a top surface across the second source/drain material, channel region material and third insulative material.

18. The method of claim 17 wherein the channel region material comprises transition metal chalcogenide.

19. The method of claim 17 wherein the channel region material comprises transition metal dichalcogenide and/or transition metal trichalcogenide.

20. The method of claim 17 wherein the channel region material comprises one or more chalcogenides selected from the group consisting of molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, indium sulfide and indium selenide.

21. The method of claim 17 wherein the channel region material is deposited at a temperature of less than or equal to about 750° C.

22. The method of claim 17 wherein the top source/drain material is patterned into top source/drain regions during the patterning into the pillars, and further comprising forming memory cells electrically coupled to the top source/drain regions.

23. The method of claim 17 wherein the top source/drain material is patterned into top source/drain regions during the patterning into the pillars, and further comprising forming charge storage devices electrically coupled to the top source/drain regions.