Overlay measuring method and system, and method of manufacturing semiconductor device using the same

1. A method of manufacturing a semiconductor device, the method comprising:

preparing a multi-layered structure of an upper pattern and a lower pattern, the lower pattern being formed by a first semiconductor process, the upper pattern being formed by a second semiconductor process;

irradiating an electron beam onto the multi-layered structure to obtain an actual image of the upper and lower patterns;

obtaining a first image representing the upper pattern and a second image representing the lower pattern from the actual image;

matching each of the first and second images and a design image of the first and second patterns to determine an overlay between the upper pattern and the lower pattern; and

compensating at least one of the first and second semiconductor processes based on the overlay measurement.

2. The method as claimed in claim 1 , wherein obtaining the actual image comprises detecting secondary electrons emitting from an upper layer in which the upper pattern is formed and detecting backscattered electrons emitting from a lower layer in which the lower pattern is formed.

3. The method as claimed in claim 1 , wherein obtaining the first image and the second image from the actual image comprises dividing the actual image according to a gray level distribution into the first image and the second image.

4. The method as claimed in claim 1 , wherein matching each of the first and second images and the design image comprises

calculating a position center for the upper pattern in the first image;

calculating a position center for the lower pattern in the second image;

determining a reference position for the upper and lower patterns from the design image; and

calculating a position deviation of the upper pattern with respect to the reference position in the first image and a position deviation of the lower pattern with respect to the reference position in the second image.

5. The method as claimed in claim 4 , wherein determining the reference position for the upper and lower patterns from the design image comprises determining a lattice point corresponding to each of the upper and lower patterns from the design image.

6. The method as claimed in claim 5 , wherein the lattice point is a common lattice which is determined from the design image of any one of the upper and lower patterns.

7. The method as claimed in claim 5 , wherein the position deviation of the upper pattern is a relative position of the upper pattern with respect to the corresponding lattice point and the position deviation of the lower pattern is a relative position of the lower pattern with respect to the corresponding lattice point.

8. The method as claimed in claim 4 , wherein calculating the position deviation of the upper pattern and the position deviation of the lower pattern comprises

sorting the upper patterns in a same layer or the lower patterns in a same layer into at least two first and second groups of patterns; and

calculating position deviations of the first and second groups of the patterns to determine an overlay between the first and second groups of the patterns.

9. The method as claimed in claim 1 , wherein the upper and lower patterns comprise one-dimensional or two-dimensional structure.

10. The method as claimed in claim 1 , wherein compensating the at least one of the first and second semiconductor processes comprises, when any one of the processes is determined to be in an abnormal process state, compensating a process parameter of the process.