IP Library › Granted Patent US 9,460,783
Granted Patent B2
US 9,460,783 · App. 14/294,802 · Granted Oct 4, 2016

Determining soft data

Inventors: Violante Moschiano (Avezzano, IT); Andrea D'Alessandro (L'Aquila, IT); Andrea Giovanni Xotta (Castelgomberto, IT)
Assignee: Micron Technology, Inc.
G11C11/5642G06F11/1012G06F11/1068G11C2029/0411
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Quick Facts
Patent No.
US 9,460,783
App. No.
14/294,802
Granted
Oct 4, 2016
Kind
B2
Abstract

The present application includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Claims (65)

1. A method for operating memory, comprising:

determining soft data associated with a data state of a memory cell;

wherein the soft data is determined by performing a single stepped sense operation on the memory cell, wherein performing the single stepped sense operation on the memory cell includes applying a single stepped sensing signal to the memory cell.

2. The method of claim 1 , wherein the method includes determining the data state of the memory cell by performing the single stepped sense operation on the memory cell.

3. The method of claim 1 , wherein:

performing the single stepped sense operation on the memory cell includes sensing a single value associated with the memory cell; and

the soft data is determined based on the single value.

4. The method of claim 1 , wherein performing the single stepped sense operation comprises performing an active sense operation.

5. An apparatus, comprising:

an array of memory cells; and

a controller configured to operate sense circuitry to:

perform a single stepped sense operation on a memory cell of the array by applying a single stepped sensing signal to the memory cell; and

determine soft data associated with a data state of the memory cell based on the single stepped sense operation.

6. The apparatus of claim 5 , wherein the controller is configured operate the sense circuitry to:

perform the single stepped sense operation to sense a current associated with the memory cell; and

determine the soft data based on the sensed current.

7. The apparatus of claim 6 , wherein the current associated with the memory cell is a current on a data line to which the memory cell is coupled.

8. The apparatus of claim 6 , wherein the controller is configured to operate the sense circuitry to determine the soft data based on the sensed current by:

determining, based on the sensed current, a voltage associated with a capacitance coupled to the memory cell during the single stepped sense operation; and

determining the soft data based on the determined voltage.

9. The apparatus of claim 8 , wherein the sense circuitry includes an analog-to-digital converter configured to convert the determined voltage to a digital value, wherein the digital value corresponds to the soft data.

10. The apparatus of claim 9 , wherein the analog-to-digital converter comprises an inverter.

11. A method for operating memory, comprising:

performing a single stepped sense operation on a memory cell to determine:

a data state of the memory cell; and

at least two soft data values associated with the data state of the memory cell;

wherein performing the single stepped sense operation on the memory cell includes applying a single stepped sensing signal to the memory cell.

12. The method of claim 11 , wherein performing the single stepped sense operation includes sensing a current associated with the memory cell, and wherein determining the data state of the memory cell and the at least two soft data values comprises:

determining, based on the sensed current, a voltage associated with a capacitance coupled to the memory cell during the single stepped sense operation; and

converting the determined voltage to a digital value, wherein the digital value corresponds to the data state and the at least two soft data values.

13. The method of claim 12 , wherein the voltage (V) associated with the capacitance coupled to the memory cell during the single stepped sense operation is given by:

V= Vcc−((Isen×tsen)/ C )

wherein Vcc is a supply voltage associated with the single stepped sense operation, Isen is the sensed current, tsen is a duration of the single stepped sense operation, and C is the capacitance.

14. The method of claim 11 , wherein the method includes correcting an error associated with the determined data state of the memory cell using the at least two soft data values.

15. The method of claim 11 , wherein the at least two soft data values indicate a location of a threshold voltage associated with the memory cell within a threshold voltage distribution associated with the data state of the memory cell.

16. The method of claim 11 , wherein the single stepped sense operation is a multilevel cell sense operation.

17. An apparatus, comprising:

an array of memory cells; and

a controller, wherein:

the controller is configured to operate sense circuitry to:

perform a single stepped sense operation on a memory cell of the array to sense a single value associated with the memory cell, wherein performing the single stepped sense operation on the memory cell includes applying a single stepped sensing signal to the memory cell; and

determine soft data values associated with a data state of the memory cell based on the single value; and

the controller includes an error correction component configured to correct an error associated with the data state of the memory cell using the determined soft data values.

18. The apparatus of claim 17 , wherein the error correction component is a low-density parity-check error correction component.

19. The apparatus of claim 17 , wherein the single value is a current associated with the memory cell.

20. The apparatus of claim 17 , wherein the controller is configured to operate the sense circuitry to determine the soft data values by:

determining, based on the single value, a voltage associated with a capacitance coupled to the memory cell during the single stepped sense operation; and

determining the soft data values based on the determined voltage.

21. An apparatus, comprising:

an array of memory cells; and

a controller configured to operate sense circuitry to:

perform a single stepped sense operation on a memory cell of the array to sense a single value associated with the memory cell, wherein performing the single stepped sense operation on the memory cell includes applying a single stepped sensing signal to the memory cell;

determine a data state of the memory cell based on the single value; and

determine at least two soft data values associated with the data state of the memory cell based on the single value.

22. The apparatus of claim 21 , wherein the controller is configured to operate the sense circuitry to determine the data state and the at least two soft data values based on a supply voltage associated with the single stepped sense operation, a duration of the single stepped sense operation, and a capacitance of a capacitance coupled to the memory cell.

23. The apparatus of claim 21 , wherein the at least two soft data values indicate a probability of whether a threshold voltage associated with the memory cell corresponds to the data state of the memory cell.

24. An apparatus, comprising:

an array of memory cells; and

a controller configured operate sense circuitry to:

perform a single stepped sense operation on a memory cell of the array by applying a single stepped sensing signal to the memory cell; and

determine at least two soft data values associated with a data state of the memory cell based on the single stepped sense operation.

25. The apparatus of claim 24 , wherein the stepped sensing signal steps down.

26. The apparatus of claim 25 , wherein the controller is configured to operate the sense circuitry to determine the at least two soft data values while the stepped sensing signal steps down.

27. The apparatus of claim 24 , wherein the stepped sensing signal steps up.

28. The apparatus of claim 27 , wherein the controller is configured to operate the sense circuitry to determine the at least two soft data values while the stepped sensing signal steps up.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2014
From: MOSCHIANO, VIOLANTE; D'ALESSANDRO, ANDREA; XOTTA, ANDREA GIOVANNI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 033091/0878 →
Continuity (1)
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