IP Library › Granted Patent US 9,461,079
Granted Patent B2
US 9,461,079 · App. 12/942,044 · Granted Oct 4, 2016

Pixel with strained silicon layer for improving carrier mobility and blue response in imagers

Inventor: Chandra Mouli (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/14603H01L27/14609
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Quick Facts
Patent No.
US 9,461,079
App. No.
12/942,044
Granted
Oct 4, 2016
Kind
B2
Abstract

An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

Claims (25)

1. A method of forming a pixel cell, the method comprising:

forming a semiconductor substrate;

forming a first silicon-germanium (SiGe) layer over the semiconductor substrate;

forming a strained silicon layer over the first SiGe layer; and

forming a buried photosensitive region of a photosensor at least in part within the semiconductor substrate and separated from the first SiGe layer by an intermediary portion of the semiconductor substrate, wherein the intermediary portion is between the first SiGe layer and the photosensitive region.

2. The method of claim 1 , wherein the first SiGe layer is graded.

3. The method of claim 2 , further comprising a step of selecting at least one of a thickness of the first SiGe layer, a molarity of the first SiGe layer, or a dopant concentration of the photosensor so as to tune at least one of the red, infra-red or near infrared absorption characteristics of the photosensor.

4. The method of claim 2 , further comprising a step of forming a second SiGe layer over the first SiGe layer.

5. The method of claim 4 , wherein the second SiGe layer is graded.

6. The method of claim 4 , wherein the second SiGe layer is formed before the strained silicon layer.

7. The method of claim 2 , wherein the photosensor is formed entirely below the strained silicon layer.

8. The method of claim 1 , wherein the photosensor comprises at least one p-type region in contact with at least one n-type region.

9. The method of claim 8 , wherein the at least one p-type region is located over the at least one n-type region.

10. The method of claim 9 , wherein the at least one p-type region is smaller in size than the at least one n-type region.

11. The method of claim 1 , wherein the photosensor is at least in part spaced from the strained silicon layer, and wherein the strained silicon layer and the photosensor at least partially overlap.

12. The method of claim 1 , further comprising forming a transfer transistor, wherein the strained silicon layer extends under the transfer transistor.

13. The method of claim 12 , further comprising forming a reset transistor, wherein the strained silicon layer extends under the reset transistor.

14. The method of claim 1 wherein the intermediary material comprises an undoped portion of the semiconductor substrate.

15. The method of claim 1 wherein forming the buried photosensitive region comprises forming a p-n junction.

16. A method of forming a pixel, the method comprising:

forming a silicon-germanium (SiGe) material over a first portion of a semiconductor substrate; and

forming a strained silicon material over the SiGe material,

wherein the first portion of the semiconductor substrate separates the SiGe and strained silicon materials from a second portion of the semiconductor substrate, and wherein the second portion of the semiconductor substrate comprises a buried photosensitive region of a photosensor.

17. The method of 16 , further comprising doping the semiconductor substrate to form the buried photosensitive region, wherein the first portion of the semiconductor substrate comprises an undoped region.

18. The method of claim 16 further comprising doping the semiconductor substrate to form a buried p-n junction.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (4)
Division 12344740 · Dec 29, 2008
Continuation 11590761 · Nov 1, 2006
Continuation 10612974 · Jul 7, 2003
Related Publication 20110059573A1 · Mar 10, 2011