Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
1. An integrated circuit, comprising:
a first plurality of interconnects, the first plurality of comprising a first pair of interconnects and a second pair of interconnects; and
a second plurality of interconnects, the second plurality comprising a third pair of interconnects and a fourth pair of interconnects;
a line of symmetry between the first plurality and the second plurality, the first plurality being disposed on a first side of the line of symmetry and the second plurality being disposed on a second side of the line of symmetry, the first and second pluralities being mirror images relative to one another across the line of symmetry along an entirety of a length of the interconnects;
wherein each interconnect of the first plurality and the second plurality comprises first ends bending towards the line of symmetry and comprises second ends that bend away from the line of symmetry;
wherein the second ends with each pair are spaced from each other by a first distance, the second ends of the first pair being spaced from the second ends of the second pair by a second distance, and the second ends of the third pair being spaced from the second ends of the fourth pair by the second distance, the second distance being greater than the first distance; and
a first bond pad associated with a first interconnect of the first pair of interconnects and a second bond pad being associated with a second interconnect of the first pair of interconnects, the first bond pad and the second bond pad associated with a second interconnect of the first pair of interconnects, the first bond pad and the second bond pad being disposed at differing distances from the line of symmetry relative to one another;
wherein the integrated circuit comprises an array region disposed between opposing periphery regions, wherein interconnects of the first and second pluralities extend into the array region from the opposing periphery regions.
2. The integrated circuit of claim 1 , wherein the interconnects comprise bond pads disposed in the periphery regions.
3. The integrated circuit of claim 1 wherein the array region is a memory array region.
4. The integrated circuit of claim 1 , wherein the interconnects are spaced between about 50 and 100 nm from one another in the array region.
5. The integrated circuit of claim 4 , wherein the interconnects are spaced between about 25 and 50 nm from one another in the array region.
6. The integrated circuit of claim 1 , wherein the interconnects comprise a metal.
7. A computer system comprising the integrated circuit of claim 1 .