Control of page access in memory
The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.
1. A controller configured to control access to a memory bank in a memory array by:
receiving a first request to access a first page in the memory bank from a first master component, wherein the memory bank comprises a plurality of pages;
in response to the first request, opening the first page in the memory bank;
receiving a second request for accessing a second page in the memory bank from a second master component; and
in response to the second request, opening the second page such that the first page and the second page are concurrently open.
2. The controller of claim 1 , wherein the controller is configured to:
determine operating conditions of the memory bank, wherein the operating conditions comprise number of concurrently open pages in the memory bank, number of master components in queue to access the memory bank, or both; and
dynamically adjust page access control method implemented to control access by the master components to the memory bank based on the operating conditions.
3. The controller of claim 1 , wherein the controller is configured to control access to the memory bank by:
receiving a third request for accessing a third page in the memory bank from a third master component; and
in response to the third request, opening the third page.
4. The controller of claim 3 , wherein the controller is configured to:
determine whether number of concurrently open pages in the memory bank is equal to a limit on number of concurrently open pages; and
close the second page before opening the third page when the number of concurrently open pages is equal to the limit on number of concurrently open pages.
5. The controller of claim 3 , wherein the controller is configured to:
determine operating duration of a transaction between the second master component and the second page;
close the second page before opening the third page when the operating duration is greater than a specific number of clock cycles.
6. The controller of claim 1 , wherein the controller is configured to:
control access to the first page using a closed page policy; and
control access to the second page using an open page policy.
7. A system, comprising:
a controller configured to control access to a memory bank in a memory array, wherein:
the memory bank comprises a plurality of pages; and
the controller is configured to enable opening more than one of the plurality of pages concurrently in the memory bank.
8. The system of claim 7 , wherein the controller is configured to dynamically adjust page access control method implemented to control access to the memory bank based on operating conditions of the memory bank.
9. The system of claim 7 , wherein the controller is configured to:
receive requests from master components to access the plurality of pages; and
provide the master components access based at least in part on the requests.
10. The system of claim 7 , wherein the controller is configured to control when each of the plurality of pages is opened or closed.
11. The system of claim 7 , wherein the system comprises a computer, a pager, a cellular phone, a personal organizer, or a control circuit.
12. A controller configured to control access to a memory bank in a memory array, wherein the controller is configured to:
determine operating conditions of the memory bank, wherein the memory bank comprises a plurality of pages;
control access of master components to the memory bank using a first page access control method when the operating conditions comprise first operating conditions; and
control access of the master components to the memory bank using a second page access control method when the operating conditions comprise second operating conditions, wherein the second operating conditions are different from the first operating conditions.
13. The controller of claim 12 , wherein the controller is configured to enable opening more than one page in the memory bank concurrently when implementing the first page access control method, the second page access control method, or both.
14. The controller of claim 12 , wherein the operating conditions comprise number of concurrently open pages in the memory bank, number of the master components in queue to access the memory bank, or both.
15. The controller of claim 14 , wherein the controller is configured to:
implement the first page access control method when the number of master components in the queue is less than a threshold; and
implement the second page access control method when the number of master components in the queue is equal to the threshold.
16. The controller of claim 12 , wherein the controller is configured to:
provide the master components access to the memory bank based at least in part on priority assigned to one or more of the master components when implementing the first page access control method; and
provide the master component access to the memory bank based at least in part on chronological order the controller receives requests from one or more of the master components when implementing the second page access control method.
17. The controller of claim 12 , wherein the controller is configured to:
close one of the plurality of pages upon completion of a transaction between one of the master components and the one of the plurality of pages when implementing the first page access control method; and
maintain the one of the plurality of pages open until a timeout of the transaction between the one of the master components and the one of the plurality of pages occurs when implementing the second page access control method.
18. The controller of claim 12 , wherein the controller is configured to:
control access to the memory bank using a closed page policy when implementing the first page access control method; and
control access to the memory bank using an open page policy when implementing the second page access control method.
19. The controller of claim 12 , wherein the controller is configured to dynamically switch between the first page access control method and the second page access control method based at least in part on the operating conditions.