IP Library Granted Patent US 9,548,360
Granted Patent B2
US 9,548,360 · App. 14/573,771 · Granted Jan 17, 2017

Semiconductor component and manufacturing method thereof

Inventor: Koichi Amari (Kanagawa, JP)
Assignee: SONY CORPORATION
H01L29/1037H01L29/4236H01L29/66545H01L29/66583H01L29/66621H01L29/7827H01L29/7834H01L29/7843
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Quick Facts
Patent No.
US 9,548,360
App. No.
14/573,771
Granted
Jan 17, 2017
Kind
B2
Abstract

A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.

Claims (50)

1. A semiconductor component comprising:

a semiconductor substrate; and

a semiconductor device on the semiconductor substrate,

wherein,

at least a portion of the semiconductor substrate has a patterned surface with a raised structure with first and second recessed portions flanking the raised structure and a third recessed portion in the raised structure,

a gate insulating film lines all surfaces of the third recessed portion,

a gate electrode within the raised structure and on the gate insulating film,

a pair of source-drain regions are in the first and second recessed portions and sandwich the raised structure, and

a pair of low-concentration impurity regions are in the raised structure and positioned between the source-drain regions and the gate electrode.

2. The semiconductor component according to claim 1 , wherein the third recessed portion has a side surface along a depth direction of the semiconductor substrate.

3. The semiconductor component according to claim 1 , wherein the third recessed portion has a surface slanted with respect to a depth direction of the semiconductor substrate.

4. The semiconductor component according to claim 1 , wherein each of source-drain regions has the same shape for the raised structure of the semiconductor substrate.

5. The semiconductor component according to claim 4 , wherein each of the source-drain regions has a flat top surface, and extends to a same depth in the semiconductor substrate in the raised structure as the third recessed portion.

6. A semiconductor component comprising:

a semiconductor substrate; and

a semiconductor device on the semiconductor substrate,

wherein

at least a portion of the semiconductor substrate has a patterned surface with a raised structure with first and second recessed portions flanking the raised structure and a third recessed portion in the raised structure,

a gate insulating film lines all surfaces of the third recessed portion,

a gate electrode within the raised structure and on the gate insulating film,

a pair of source-drain regions are in the first and second recessed portions and sandwich the raised structure,

the third recessed portion has a surface slanted with respect to a depth direction of the semiconductor substrate, and

the slanted surface of the third recessed portion lies on a (111) plane.

7. A method for manufacturing a semiconductor component, the method comprising the steps of:

providing a semiconductor substrate with at least a portion of the semiconductor substrate being a patterned surface and having a raised structure flanked by first and second recessed regions and with a third recessed portion in the raised structure,

lining all the interior surfaces of the third recessed portion with a gate insulating film,

providing a gate electrode within the third recessed portion on the gate insulating film,

providing a pair of source-drain regions on the semiconductor substrate so as to sandwich the raised structure, and

providing a pair of low-concentration impurity regions in the raised structure between the source-drain regions and the gate electrode.

8. The method of claim 7 , wherein:

the third recessed portion has a surface slanted with respect to a depth direction of the semiconductor substrate, and

the slanted surface of the third recessed portion lies on a (111) plane.

9. A method for manufacturing a semiconductor component, the method comprising the steps of:

providing a semiconductor substrate with at least a portion of the semiconductor substrate being a patterned surface and having a raised structure flanked by first and second recessed regions and with a third recessed portion in the raised structure,

lining all the interior surfaces of the third recessed portion with a gate insulating film,

providing a gate electrode within the third recessed portion on the gate insulating film, and

providing a pair of source-drain regions on the semiconductor substrate so as to sandwich the raised structure,

providing a dummy gate electrode via a dummy gate insulating film on a surface of the semiconductor substrate in a portion of the semiconductor substrate where the gate insulating film and the gate electrode of the semiconductor device are to be provided;

providing a planarizing film on the surface of the semiconductor substrate so as to expose a top surface of the dummy gate electrode, and to cover a top surface of the pair of source-drain regions;

removing the dummy gate electrode and the dummy gate insulating film so as to expose the semiconductor substrate on the surface from which the dummy gate electrode and the dummy gate insulating film are removed, and to form an opening in the exposed surface portion;

etching the opening surface of the semiconductor substrate to provide the first, second, and third recessed portions and form the patterned surface on the semiconductor substrate;

providing an insulating film over the patterned surface of the semiconductor substrate so as to form the gate insulating film; and

providing a conductive film over the gate insulating film formed on the patterned surface so as to form the gate electrode.

10. A method for manufacturing a semiconductor component, the method comprising the steps of:

providing a semiconductor substrate with at least a portion of the semiconductor substrate being a patterned surface and having a raised structure flanked by first and second recessed regions and with a third recessed portion in the raised structure,

lining all the interior surfaces of the third recessed portion with a gate insulating film,

providing a gate electrode within the third recessed portion on the gate insulating film, and

providing a pair of source-drain regions on the semiconductor substrate so as to sandwich the raised structure,

wherein,

the pair of source-drain regions is formed in the same shape as the raised structure and the third recessed portion of the semiconductor substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2015
From: AMARI, KOICHI
To: SONY CORPORATION
Reel/Frame 034746/0111 →
Priority Claims (1)
JP 2009-298319 · Dec 28, 2009 · national
Continuity (2)
Continuation 12967857 · Dec 14, 2010
Related Publication 20150102402A1 · Apr 16, 2015