Trench formation with CD less than 10nm for replacement fin growth
Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.
1. A method of forming a semiconducting fin structure, comprising:
etching a first layer to form a feature bounded by a first material;
depositing a second layer over the first material and the feature formed in the first layer;
etching the second layer to expose a portion of the first layer within the feature through the second layer; and
forming a III-V material on the exposed portion of the first layer, the III-V material filling the feature between the second layer.
2. The method of claim 1 , wherein the feature has an aspect ratio of between about 5:1 and about 30:1.
3. The method of claim 1 , wherein the III-V material has a critical dimension of less than about 10 nm.
4. The method of claim 1 , further comprising:
removing a portion of the first material, the second layer, and the III-V material to form a planar surface.
5. The method of claim 1 , wherein the first layer is a semiconductive material.
6. The method of claim 5 , wherein the first material and the second layer are insulator materials.
7. The method of claim 6 , wherein the second layer is conformally deposited over the first material and the feature formed in the first material.
8. A method of forming a semiconducting fin structure, comprising:
etching a semiconductive layer to form a feature bounded by a first insulator material;
depositing a second insulator material over the first insulator material and the feature formed in the semiconductive layer;
etching the second insulator material to expose a portion of the semiconductive layer within the feature through the second insulator material; and
forming a semiconducting material on the exposed portion of the semiconductive layer, the semiconducting material filling the feature between the second insulator material.
9. The method of claim 8 , wherein the feature has an aspect ratio of between about 5:1 and about 30:1 and the semiconducting material has a critical dimension of less than about 10 nm.
10. The method of claim 8 , further comprising:
removing a portion of the first insulator material, the second insulator material, and the semiconducting material to form a planar surface.
11. The method of claim 8 , wherein the second insulator material is conformally deposited over the first insulator material and the feature formed in the semiconductive layer.
12. The method of claim 8 , further comprising:
etching a first region of a photoresist layer to expose a first region of a neutral layer; and
etching the exposed region of the neutral layer to expose a first region of a hardmask layer.
13. The method of claim 8 , further comprising:
etching a hardmask layer to expose a first region of the semiconductive layer; and
etching the first region of the semiconductive layer to form a trench.
14. The method of claim 13 , further comprising:
depositing the first insulator material in the trench.
15. The method of claim 8 , wherein the semiconducting material comprises a III-V material having a critical dimension of less than about 10 nm.
16. A method of forming a semiconducting fin structure, comprising:
etching a silicon layer to form a feature bounded by an insulator material;
depositing a dielectric layer over the insulator material and the feature formed in the silicon layer;
etching the dielectric layer to expose a portion of the silicon layer within the feature through the dielectric layer; and
forming a semiconducting material on the exposed portion of the silicon layer, the semiconducting material filling the feature between the dielectric layer.
17. The method of claim 16 , wherein the feature has an aspect ratio of between about 5:1 and about 30:1 and the semiconducting material comprises a III-V material having a critical dimension of less than about 10 nm.
18. The method of claim 16 , further comprising:
removing a portion of the insulator material, the dielectric material, and the semiconducting material to form a planar surface.
19. The method of claim 16 , wherein the dielectric layer is conformably deposited over the insulator material and the feature formed in the silicon layer.
20. The method of claim 16 , further comprising:
etching a first region of a photoresist layer to expose a first region of a neutral layer;
etching the exposed region of the neutral layer to expose a first region of a hardmask layer;
etching the exposed region of the hardmask layer to expose a first region of the silicon layer;
etching a second region of the photoresist layer and a second region of the neutral layer to expose a second region of the hardmask layer;
etching the first region of the silicon layer to form a trench;
depositing the insulator material in the trench;
planarizing the second region of the hardmask layer and the insulator material;
implanting ions into a second region of the silicon layer and the insulator material; and
etching the second region of the hardmask layer to expose the second region of the silicon layer.