Epitaxially grown stacked contact structure of semiconductor device

1. A method of forming a semiconductor device structure, comprising:

forming a gate structure formed over a surface of a semiconductor substrate;

forming a recess neighboring the gate structure, wherein the recess is formed below the surface of the semiconductor substrate; and

forming a strained material stack filling the recess, wherein the strain material stack comprises a first SiGe layer, a graded SiGe layer, a boron-doped (B-doped) germanium (GeB) layer, a Ge layer, and a second SiGe layer.

2. The method of claim 1 , wherein the step of forming a recess neighboring the gate structure includes:

etching the semiconductor substrate isotropically using a dry etch process; and

further etching the semiconductor substrate using a wet etch process.

3. The method of claim 1 , further comprising:

forming a contact structure formed in an inter-layer dielectric (ILD) layer;

depositing a metal layer and a protective layer sequentially over the contact structure; and

performing a thermal annealing to drive metal in the metal layer into the second SiGe layer and the Ge layer.

4. The method of claim 3 , the metal layer comprises Ti, Al, Mo, Zr, Hf, Ta, In, Ni, Be, Mg, Ca, Y, Ba, Sr, Sc, or Ga.

5. The method of claim 3 , further comprising:

performing a wet etch to remove the protective layer and un-reacted metal of the metal layer.

6. The method of claim 3 , wherein after the thermal anneal the second SiGe layer becomes a metal-SiGe layer and at least a portion of the Ge layer becomes a metal-Ge layer.

7. The method of claim 6 , wherein another portion of the Ge layer remains un-reacted.

8. A method of forming a semiconductor device structure, comprising:

forming a gate stack formed over a surface of a semiconductor substrate;

etching a source recess and a drain recess adjacent opposite sidewalls of the gate stack;

epitaxially growing a first Ge-containing layer in the source recess and in the drain recess to a first thickness;

epitaxially growing a second Ge-containing layer, in the source recess and in the drain recess to a second thickness, the second Ge-containing layer having a graded Ge concentration;

epitaxially growing a third Ge-containing layer in the source recess and in the drain recess to a second thickness, the third Ge-containing layer being doped with a dopant; and

epitaxially growing a fourth Ge-containing layer in the source recess and in the drain recess, the fourth Ge-containing layer having the same composition as the first Ge-containing layer.

9. The method of claim 8 , further comprising epitaxially growing a Ge layer on the third Ge-containing layer before epitaxially growing the fourth Ge-containing layer.

10. The method of claim 8 wherein the second Ge-containing layer is SiGe with a Ge concentration of about 30% at a bottom of the second Ge-containing layer and about 80% at a top of the second Ge-containing layer.

11. The method of claim 8 , further comprising:

forming a dielectric layer over the gate stack;

removing the gate stack; and

forming a replacement gate stack in place of the removed gate stack.

12. The method of claim 8 , further comprising:

depositing a dielectric layer over the fourth Ge-containing layer;

patterning the dielectric layer to form an opening therein exposing a portion of the fourth Ge-containing layer;

depositing a metal layer on the exposed portion of the fourth Ge-containing layer; and

reacting the metal layer and the fourth Ge-containing layer to form a contact structure.

13. The method of claim 12 , further comprising forming a protective layer over the metal containing layer before the step of reacting the metal layer with the fourth Ge-containing layer.

14. The method of claim 12 wherein the step of reacting the metal layer and the fourth Ge-containing layer comprises annealing the layers to form metal silicide and metal germanide compounds.

15. A method of forming a semiconductor device structure, comprising:

forming a dummy gate structure formed over a surface of a semiconductor substrate;

forming a recess neighboring the dummy gate structure, wherein the recess is formed below the surface of the semiconductor substrate;

filling the recess with a strained material stack wherein the strain material stack comprises a first Si-compound layer, a graded Si-compound layer atop the first Si-compound layer, a doped layer atop the graded Si-compound layer, and a second Si-compound layer overlying the doped layer; and

reacting the second Si-compound layer with a metal layer to form a metal silicide.

16. The method of claim 15 further comprising an undoped layer atop the doped layer and underlying the second Si-compound layer.

17. The method of claim 15 wherein the Si-compound layer is selected from the group consisting of SiGe, SiC, and SiP.

18. The method of claim 15 wherein the doped layer is a Ge layer doped with a p-type dopant.

19. The method of claim 15 wherein the graded Si-compound layer is a graded SiGe layer having a Ge concentration that varies from a high level at a top surface of the layer to a low level at a bottom surface of the layer.

20. The method of claim 15 further comprising removing the dummy gate structure and replacing the dummy gate structure with a replacement gate structure.