Memory controller for strobe-based memory systems
An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.
1. A memory controller comprising:
a first receiver to receive read data;
a second receiver to receive a strobe signal, wherein the strobe signal is sent by a DRAM, along with the read data;
a circuit to establish a phase alignment between a read enable signal and the strobe signal;
a mask circuit to generate a masked strobe signal based on the phase alignment; and
sampling circuitry to sample the read data based on the masked strobe signal.
2. The memory controller according to claim 1 , wherein the circuit to establish the phase alignment comprises a delay circuit.
3. The memory controller according to claim 2 , wherein the phase offset is applied to the read enable signal.
4. The memory controller according to claim 3 , wherein application of the phase offset to the read enable signal places a transitioning edge of the read enable signal relative to a valid portion of the strobe signal.
5. The memory controller according to claim 2 , wherein the phase offset is based on a value that is retrieved from storage.
6. The memory controller according to claim 5 , wherein the storage comprises a programmable register.
7. The memory controller according to claim 5 , wherein the value is determined during a calibration mode of operation.
8. An integrated circuit (IC) chip comprising:
control circuitry for controlling memory access operations between the IC chip and a DRAM chip;
a first receiver to receive read data;
a second receiver to receive a strobe signal, wherein the strobe signal is sent by the DRAM, along with the read data;
a phase alignment circuit to establish a desired timing relationship between a read enable signal and the strobe signal;
a mask signal to generate a masked strobe signal based on the desired timing relationship; and
sampling circuitry to sample the read data based on the masked strobe signal.
9. The IC chip according to claim 8 , wherein the delay circuit is to apply a delay to the read enable signal to establish the timing relationship.
10. The IC chip according to claim 9 , wherein the delay is based on a value retrieved from storage.
11. The IC chip according to claim 10 , wherein the storage comprises a programmable register.
12. The IC chip according to claim 10 , wherein the value is determined during a calibration mode of operation.
13. The IC chip according to claim 9 , wherein application of the delay to the read enable signal places a transitioning edge of the read enable signal relative to a valid portion of the strobe signal.
14. A method of operation in an integrated circuit (IC) memory controller, the method comprising:
receiving read data with a first receiver;
receiving a strobe signal with a second receiver, wherein the strobe signal is sent by a DRAM, along with the read data;
establishing a phase alignment between a read enable signal and the strobe signal;
generating a masked strobe signal based on the phase alignment; and
sampling the read data based on the masked strobe signal.
15. The method according to claim 14 , wherein the establishing a phase alignment comprises applying a phase offset.
16. The method according to claim 15 , wherein the applying a phase offset is applied to the read enable signal.
17. The method according to claim 16 , wherein the applying of the phase offset to the read enable signal places a transitioning edge of the read enable signal relative to a valid portion of the strobe signal.
18. The method according to claim 15 , wherein the applying of the phase offset includes retrieving a value from storage, and wherein the phase offset is based on the value.
19. The method according to claim 15 , wherein the retrieving of the value from storage comprises retrieving the value from a programmable register.
20. The method according to claim 15 , wherein the value is determined during a calibration mode of operation.