IP Library Granted Patent US 9,570,370
Granted Patent B2
US 9,570,370 · App. 14/460,734 · Granted Feb 14, 2017

Multi chip package and method for manufacturing the same

Inventors: Tac Keun Oh (Seoul, KR); Jong Hoon Kim (Suwon, KR); Ho Young Son (Cheongwon, KR); Jeong Hwan Lee (Seoul, KR)
Assignee: SK HYNIX INC.
H01L23/36H01L21/486H01L21/4871H01L21/56H01L23/34H01L23/49827H01L23/5384H01L23/5385H01L25/0657H01L23/3128H01L23/42H01L2224/16225H01L2224/32225H01L2224/73204H01L2924/15311H01L2924/181H01L2924/18161
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Quick Facts
Patent No.
US 9,570,370
App. No.
14/460,734
Granted
Feb 14, 2017
Kind
B2
Abstract

A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces.

Claims (19)

1. A method for manufacturing a multi chip package, the method comprising:

mounting a first chip and a second chip over an upper surface of a first substrate;

forming a protective layer that covers the first chip and the second chip;

removing a part of an upper side of the protective layer and a part of upper sides of the first chip and the second chip by planarizing an upper surface of the first chip, an upper surface of the second chip, and an upper surface of the protective layer to form a global planar surface;

grinding the global planar surface to form rough surfaces of convex and concave shapes;

forming a thermal interface material over the upper surface of the first chip, over the upper surface of the second chip, and over the upper surface of the protective layer; and

attaching a heat spreader to the thermal interface material,

wherein the first substrate has an interposer structure including a first interconnection part, a second interconnection part, and a through electrode,

wherein the first chip is positioned beside the second chip over the interposer structure,

wherein the second interconnection part has a horizontal connection structure to connect the first chip and the second chip, and

wherein the first interconnection part connects the first chip to the through electrode.

2. The method of claim 1 , wherein a function performed by the first chip is different from a function performed by the second chip.

3. The method of claim 1 , wherein the first chip includes at least two vertically stacked memory chips; and

wherein the second chip includes a graphic processing unit (GPU), a central processing unit (CPU), or a system on chip (SoC).

4. The method of claim 1 , further comprising:

positioning a vertical stiffener between the heat spreader and the first substrate to support the heat spreader.

5. The method of claim 1 , further comprising:

mounting the first substrate on a second substrate before attaching a heat spreader to the thermal interface material; and

positioning a vertical stiffener between the heat spreader and the second substrate to support the heat spreader.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2014
From: OH, TAC KEUN; KIM, JONG HOON; SON, HO YOUNG; LEE, JEONG HWAN
To: SK HYNIX INC.
Reel/Frame 033552/0483 →
Priority Claims (1)
KR 10-2014-0061663 · May 22, 2014 · national
Continuity (1)
Related Publication 20150340303A1 · Nov 26, 2015