Recessing RMG metal gate stack for forming self-aligned contact
Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.
1. A structure comprising:
a gate dielectric layer on a substrate;
a work-function metal layer on the gate dielectric layer, the work-function metal layer having an upper surface that is substantially flush with an upper surface of the gate dielectric layer;
a gate electrode on the upper surface of the gate dielectric layer and the upper surface of the work-function metal layer;
a gate cap above the gate electrode, the gate cap having an upper surface that is substantially flush with an upper surface of a spacer that is adjacent to the gate cap, the gate electrode, and the gate dielectric layer; and
a first embedded etch stop layer embedded in the spacer, the first embedded etch stop comprising dopant atoms.
2. The structure of claim 1 , further comprising:
a second embedded etch stop layer between the gate electrode and the gate cap, the second embedded etch stop layer extending laterally into the spacer and comprising dopant atoms.
3. The structure of claim 1 , further comprising:
an interlevel dielectric (ILD) layer on the substrate adjacent to the spacer, the ILD layer having an upper surface that is substantially flush with an upper surface of the gate cap;
an upper dielectric layer formed on the gate cap, the spacer, and the ILD layer;
an electrical contact extending through the upper dielectric layer and the ILD layer, wherein the electrical contact is in contact with the gate cap, the spacer, and an upper surface of a source-drain region that is adjacent to the spacer.
4. The structure of claim 1 , wherein the first embedded etch stop layer is located between a top insulating material layer and a bottom insulator material layer that comprise the spacer.
5. The structure of claim 1 , wherein the dopant atom of the first embedded etch stop layer comprises silicon, carbon, or nitrogen.
6. The structure of claim 1 , wherein an inner sidewall of the first embedded etch stop layer contacts an outer sidewall of the gate electrode.
7. The structure of claim 1 , wherein a topmost surface of the first embedded etch stop layer is coplanar with a topmost surface of the gate electrode.
8. The structure of claim 1 , wherein the work-function metal layer comprises a stack of a first work-function metal layer, a second work-function metal layer and a third work-function metal layer.
9. The structure of claim 8 , wherein the first work-function metal layer and the and the second work-function metal layer are both U-shaped, and have a topmost surface that is coplanar with a topmost surface of the gate dielectric layer.
10. The structure of claim 1 , wherein the gate electrode has outermost sidewalls that are vertical aligned with outermost sidewalls of the gate dielectric layer.
11. The structure of claim 1 , wherein a second embedded etch stop layer comprising a dopant atom is located above the first embedded etch stop layer and is entirely embedded in the spacer.
12. The structure of claim 11 , wherein the second embedded etch stop layer has an inner sidewall that contacts the gate cap.
13. The structure of claim 11 , wherein the second embedded etch stop layer is located between a top insulating material layer of the spacer and a bottom insulator material layer of the spacer.
14. The structure of claim 11 , wherein the dopant atom of the second embedded etch stop layer comprises silicon, carbon, or nitrogen.
15. The structure of claim 11 , wherein the second embedded etch stop layer has a bottommost surface that is coplanar with a bottommost surface of the gate gap.