Multi-device memory serial architecture
Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.
1. A method of operating a memory device, the method comprising:
determining a particular memory device of a plurality of memory devices, connected via a chain topology comprising serial bidirectional interconnections between memory devices, to electronically access based on a command from a processor;
transmitting at least one signal from a memory controller directly via a conducting line to a switch within the particular memory device, wherein the conducting line is separate from the bidirectional interconnections;
electrically connecting a memory array of the particular memory device to a bidirectional interconnection interface of the particular memory device in response to the at least one signal while electrically disconnecting a memory array of a memory device between the memory controller and the particular memory device; and
while the memory of the memory device between the memory controller and the particular memory device is electrically disconnected, electrically connecting the memory array of the particular memory device indirectly to the memory controller via the bidirectional interconnections through the memory device between the memory controller and the particular memory device.
2. The method of claim 1 , wherein the command comprises a read, write, or erase instruction.
3. The method of claim 1 , wherein determining the particular memory device comprises determining which memory device of the plurality of memory devices to access based at least in part on a memory address provided with the command.
4. The method of claim 1 , wherein the signal comprises a multibit digital signal designating the memory array.
5. The method of claim 1 , wherein electrically connecting and electrically disconnecting comprises switching via a switch within each of the plurality of memory devices configured to directly interface the memory controller via an individual conducting line for each of the plurality of memory devices.
6. The method of claim 1 , wherein the switch comprises a micro-electro-mechanical (MEM) switch.
7. A method for operating a memory device, the method comprising:
providing a command, having at least a memory device address, from a processor to a memory controller;
selecting a particular memory device from a plurality of interconnected memory devices based on the memory device address of the command, wherein the particular memory device is indirectly connected to the memory controller via bidirectional interconnections through a memory device between the memory controller and the particular memory device;
transmitting a signal from the memory controller directly via a conducting line not connected to the bidirectional interconnections to a switch within the particular memory device to connect a memory array of the particular memory device to the memory controller via the bidirectional interconnections; and
disconnecting a memory array of the memory device between the memory controller and the particular memory device from the memory controller.
8. The method of claim 7 , wherein the command comprises a read, write, or erase instruction.
9. The method of claim 7 , wherein each of the plurality of interconnected memory devices comprises a switch for connecting and disconnecting each of the plurality of interconnected memory devices from the memory controller.
10. The method of claim 7 , wherein the memory device is selected from the group consisting of DRAM, NAND flash memory, NOR flash memory, and phase change memory.
11. The method of claim 7 , wherein the disconnected memory array of the memory devices is electrically isolated from the memory controller.
12. A method for operating a memory device, the method comprising:
processing a command, having at least a memory device address, from a processor to a memory controller; and
selecting, based on the memory device address of the command, a particular memory device (M 1 ) from a plurality of interconnected memory devices (Mn) by transmitting a signal from the memory controller directly via a conducting line to a switch within the particular memory device; and wherein;
in response to directly transmitting the signal to the switch, a memory array of the particular memory device is connected to the memory controller and a memory array of each memory device other than the particular memory device is disconnected from the memory controller;
the particular memory device is electrically connected indirectly via bidirectional interconnections to the memory controller through another memory device between the memory controller and the particular memory device; and
the conducting line is not connected to the bidirectional interconnections.
13. The method of claim 12 , wherein the plurality of interconnected memory devices are incorporated into a computer, a cell phone, a personal data assistant, a data logger, or navigational equipment.
14. The method of claim 12 , wherein each of the plurality of interconnected memory devices comprises the switch further configured for connecting and disconnecting each of the plurality of interconnected memory devices.
15. The method of claim 12 , wherein each of the plurality of interconnected memory devices comprises the switch further configured for connecting a frontside bidirectional interconnection interface to a backside bidirectional interconnection interface.
16. The method of claim 12 , wherein each of the plurality of interconnected memory devices comprises the switch further configured for buffering signals.