Recessed lead leadframe packages
Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads where the plurality of leads except for at least one are configured to mechanically couple at a surface of a semiconductor chip. The at least one of the plurality of leads that is not configured to mechanically coupled at the surface of the semiconductor chip be configured to electrically couple with the semiconductor chip.
1. A leadframe for use in a chip-on-lead package, the leadframe comprising:
the leadframe including a plurality of leads extending inwardly into an opening surrounded by the plurality of leads;
one of the plurality of leads contains a thinned lead and does not extend into the opening as far as the other leads of the plurality of leads;
wherein the plurality of leads are configured to directly mechanically couple at a surface of a semiconductor chip;
wherein the thinned lead is configured to not directly mechanically couple at the surface of the semiconductor chip; and
wherein the thinned lead comprises a thinned portion across a thickness of the thinned lead adjacent to the semiconductor chip and is configured to electrically couple with the semiconductor chip.
2. The leadframe of claim 1 , wherein the thinned portion of the thinned lead is one of half etched and fully etched.
3. The leadframe of claim 1 , wherein the thinned lead is configured to carry a high voltage signal to the semiconductor chip.
4. The leadframe of claim 1 , wherein the plurality of leads are configured to mechanically support the semiconductor chip through coupling at the surface of the semiconductor chip through a die bonding material.
5. The leadframe of claim 4 wherein the thinned lead is not mechanically coupled at the surface of the semiconductor chip through the die bonding material.
6. The leadframe of claim 1 , wherein the plurality of leads are configured to couple with an electronic circuit board at a surface of each of the plurality of leads opposite the surface of the semiconductor chip.
7. The leadframe of claim 6 , wherein a perimeter of the surface of each of the plurality of leads opposite the surface of the semiconductor chip is smaller than a perimeter of a surface of each of the plurality of leads configured to be coupled at the surface of the semiconductor chip.
8. The leadframe of claim 7 , wherein the surface of each of the plurality of leads except for the thinned lead opposite the surface of the semiconductor chip is one of half etched and fully etched.