Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.
1. A method of processing semiconductor devices, comprising:
forming grooves partially through a molding material, the molding material located in streets of a wafer-level assembly comprising laterally separated stacks of semiconductor dice on a wafer, a carrier substrate supporting the wafer on a side of the wafer opposite the stacks of semiconductor dice;
heating the wafer-level assembly while the grooves remain unoccupied; and
detaching the carrier substrate from the wafer while heating the wafer-level assembly.
2. The method of claim 1 , wherein heating the wafer-level assembly comprises heating the wafer-level assembly to a temperature in excess of 200° C. while maintaining warpage of the wafer-level assembly to no more than about 1 mm as determined by adding a largest positive displacement of a surface of the wafer-level assembly and a largest negative displacement of the surface of the wafer-level assembly with respect to a plane defined by a least-squares fit of the surface of the wafer-level assembly.
3. The method of claim 1 , wherein heating the wafer-level assembly comprises heating the wafer-level assembly to a temperature in excess of 200° C. while maintaining the warpage of the wafer to no more than about 0.75 mm as determined by adding a largest positive displacement of a surface of the wafer-level assembly and a largest negative displacement of the surface of the wafer-level assembly with respect to a plane defined by the least-squares fit of the surface of the wafer-level assembly.
4. The method of claim 1 , wherein forming the grooves comprises forming the grooves to a depth of between about 20% to about 80% of a height of the molding material above the wafer.
5. The method of claim 1 , wherein forming the grooves comprises forming the grooves to a depth of about 50% of a height of the molding material above the wafer.
6. The method of claim 1 , wherein forming the grooves comprises forming the grooves to a depth of between about 25% to about 75% of a height of the stacks of semiconductor dice above the wafer.
7. The method of claim 1 , wherein forming the grooves comprises forming the grooves to a depth of about 50% of a height of the stacks of semiconductor dice above the wafer.
8. The method of claim 1 , wherein heating the wafer-level assembly comprises heating the wafer-level assembly to a temperature of 200° C. or higher to detach the carrier substrate from the wafer.
9. The method of claim 1 , further comprising disposing the molding material over the stacks of semiconductor dice and in the streets before forming the grooves.
10. The method of claim 1 , further comprising removing the molding material over the stacks of semiconductor dice to expose tops of the stacks before forming the grooves.
11. The method of claim 1 , wherein heating the wafer-level assembly comprises heating the wafer-level assembly to a temperature of 200° C. or higher, and further comprising permitting the wafer-level assembly to cool to room temperature and cutting through the molding material and wafer along the streets and where grooves exist, coincident with the grooves, to separate individual stacks of semiconductor dice from one another.
12. The method of claim 11 , wherein cutting through the molding material and wafer along the streets comprises cutting a narrower width than a width of the grooves.
13. The method of claim 1 , wherein forming the grooves comprises forming the grooves in fewer than all streets.
14. The method of claim 1 , wherein forming the grooves comprises forming the grooves corresponding to at least substantially all streets.
15. A wafer-level method of preparing semiconductor devices, comprising:
attaching a wafer to a carrier substrate with an adhesive comprising a thermoplastic material;
forming semiconductor die stacks over die locations on the wafer on a side of the wafer opposite the carrier;
disposing molding material over the die stacks and in streets between the die stacks on the wafer;
partially cutting through the molding material to form grooves in the streets;
exposing the wafer, die stacks, and molding material to an elevated temperature while the grooves remain free of occupying material; and
detaching the carrier substrate from the wafer while exposing the wafer, die stacks, and molding material to the elevated temperature.
16. The method of claim 15 , wherein exposing the wafer, die stacks, and molding material to the elevated temperature comprises exposing the wafer, die stacks, and molding material to a temperature of 200° C. or higher to soften the thermoplastic material.
17. The method of claim 15 , further comprising, at a temperature of about 200° C., maintaining a warpage of the wafer to about 1 mm or less as measured by adding a largest positive displacement of a surface of the wafer-level assembly and a largest negative displacement of the surface of the wafer-level assembly with respect to a plane defined by a least-squares fit of the surface of the wafer-level assembly.
18. The method of claim 15 , further comprising, at a temperature of about 200° C., maintaining a warpage of the wafer to about 0.75 mm or less as measured by adding a largest positive displacement of a surface of the wafer-level assembly and a largest negative displacement of the surface of the wafer-level assembly with respect to a plane defined by a least-squares fit of the surface of the wafer-level assembly.
19. The method of claim 15 , wherein forming the grooves in the streets defined by the molding material comprises forming the grooves to a depth of between about 25% to about 75% of a height of the die stacks above the wafer.
20. The method of claim 15 , wherein forming the grooves in the streets defined by the molding material comprises forming the grooves to a depth of between about 20% to about 80% of a height of the molding material above the wafer.