IP Library Granted Patent US 9,594,676
Granted Patent B2
US 9,594,676 · App. 14/513,880 · Granted Mar 14, 2017

Configuring and reconfiguring blocks of memory cells to store user data and ECC data

Inventors: William H. Radke (Los Gatos, CA); Tommaso Vali (Latina, IT); Michele Incarnati (Gioia dei Marsi, IT)
Assignee: Micron Technology, Inc.
G06F12/0646G06F3/0608G06F3/0631G06F3/0679G06F11/1048G06F11/1068G06F12/0207G11C16/0483G11C16/10G11C11/5628
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,594,676
App. No.
14/513,880
Granted
Mar 14, 2017
Kind
B2
Abstract

A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of memory cells in a second configuration comprising one or more groups of user data memory cells and at least one group of overhead data memory cells. The first configuration is different than the second configuration. At least one group of overhead data memory cells of the second block of memory cells comprises a different storage capacity than at least one group of overhead data memory cells of the first block of memory cells.

Claims (40)

1. A memory device, comprising:

a plurality of individually erasable blocks of memory cells; and

a controller configured to configure a first block of the plurality of individually erasable blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of the plurality of individually erasable blocks of memory cells in a second configuration comprising one or more groups of user data memory cells to store first user data and at least one group of overhead data memory cells to store a first portion of ECC data that is specific to the first user data, wherein at least one group of the overhead data memory cells of the one or more groups of overhead data memory cells of the first block of the plurality of individually erasable blocks of memory cells is to store a second portion of the ECC data that is specific to the first user data, wherein the first and second portions of the ECC data that is specific to the first user data comprises all ECC data that is specific to the first user data;

wherein the first configuration is different than the second configuration;

wherein the at least one group of overhead data memory cells of the second block of the plurality of individually erasable blocks of memory cells comprises a different storage capacity than the at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of the plurality of individually erasable blocks of memory cells;

wherein the controller being configured to configure the second block of the plurality of individually erasable blocks of memory cells in the second configuration comprises the controller being configured to reconfigure the second block of the plurality of individually erasable blocks of memory cells to the second configuration from a third configuration comprising the one or more groups of user data memory cells of the second configuration and the at least one group of overhead data memory cells of the second configuration to store second user data; and

wherein the controller being configured to configure the first block of the plurality of individually erasable blocks of memory cells in the first configuration comprises the controller being configured to reconfigure the first block to the first configuration from a fourth configuration comprising a group of overhead data memory cells to store all ECC data specific to the second user data.

2. The memory device of claim 1 , further comprising a plurality of memory die, each memory die comprising one or more individually erasable blocks of memory cells.

3. The memory device of claim 1 , wherein the controller is configured to configure space allocation of the first block of the plurality of individually erasable blocks of memory cells independently from the second block of the plurality of individually erasable blocks of memory cells.

4. The memory device of claim 1 , wherein the controller comprises a non-volatile memory in which memory array configuration data is stored.

5. The memory device of claim 1 , wherein the first user data has a different space requirement than the second user data.

6. The memory device of claim 1 , wherein the ECC data that is specific to the first user data has a different space requirement than the ECC data that is specific to the second user data.

7. The memory device of claim 1 , wherein each of the first and second blocks of the plurality of individually erasable blocks of memory cells is arranged into one or more pages of memory cells.

8. The memory device of claim 7 , wherein each of the one or more pages of memory cells of each of the first and second blocks of the plurality of individually erasable blocks of memory cells is arranged into one or more sectors.

9. The memory device of claim 1 , wherein the controller is configured to determine a space requirement for the ECC data that is specific to the first user data.

10. The memory device of claim 1 , wherein the controller is configured to program the user data memory cells of the one or more groups of user data memory cells of the second configuration that are in the third configuration and the overhead data memory cells of the at least one group of overhead data memory cells of the second configuration that is in the third configuration as multilevel memory cells, and wherein the controller is configured to program the overhead data memory cells of the group of overhead data memory cells to store all ECC data specific to the second user data as single-level memory cells.

11. A memory device, comprising:

a plurality of individually erasable blocks of memory cells; and

a controller configured to configure a first block of the plurality of individually erasable blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of the plurality of individually erasable blocks of memory cells in a second configuration comprising one or more groups of user data memory cells to store first user data and at least one group of overhead data memory cells to store a first portion of ECC data that is specific to the first user data, wherein at least one group of the overhead data memory cells of the one or more groups of overhead data memory cells of the first block of the plurality of individually erasable blocks of memory cells is to store a second portion of the ECC data that is specific to the first user data, wherein the first and second portions of the ECC data that is specific to the first user data comprises all ECC data that is specific to the first user data;

wherein the first configuration is different than the second configuration;

wherein the at least one group of overhead data memory cells of the second block of the plurality of individually erasable blocks of memory cells comprises a different storage capacity than the at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of the plurality of individually erasable blocks of memory cells;

wherein the controller being configured to configure the second block of the plurality of individually erasable blocks of memory cells in the second configuration comprises the controller being configured to reconfigure the second block of the plurality of individually erasable blocks of memory cells to the second configuration from a third configuration comprising the one or more groups of user data memory cells of the second configuration and the at least one group of overhead data memory cells of the second configuration to store second user data;

wherein the controller being configured to configure the first block of the plurality of individually erasable blocks of memory cells in the first configuration comprises the controller being configured to reconfigure the first block to the first configuration from a fourth configuration comprising a group of overhead data memory cells to store all ECC data specific to the second user data; and

wherein the controller is configured to use an ECC scheme to determine the ECC data that is specific to the first user data.

12. The memory device of claim 11 , wherein the controller is configured to use a different ECC scheme to determine the ECC data that is specific to the second user data than the ECC scheme used to determine the ECC data that is specific to the first user data.

13. The memory device of claim 11 , wherein the ECC scheme comprises one of a Hamming code, BCH code, Reed-Solomon code, Reed-Muller code, Binary Golay code, Low-Density Parity Code, or Trellis Code modulation code.

14. The memory device of claim 11 , wherein each of the first and second blocks is arranged into one or more pages of memory cells.

15. The memory device of claim 11 , wherein the first user data has a different space requirement than the second user data.

16. The memory device of claim 11 , wherein the ECC data that is specific to the first user data has a different space requirement than the ECC data that is specific to the second user data.

17. A memory device, comprising:

a plurality of individually erasable blocks of memory cells; and

a controller configured to configure a first block of the plurality of individually erasable blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of the plurality of individually erasable blocks of memory cells in a second configuration comprising one or more groups of user data memory cells to store first user data and at least one group of overhead data memory cells to store a first portion of ECC data that is specific to the first user data, wherein at least one group of the overhead data memory cells of the one or more groups of overhead data memory cells of the first block of the plurality of individually erasable blocks of memory cells is to store a second portion of the ECC data that is specific to the first user data, wherein the first and second portions of the ECC data that is specific to the first user data comprises all ECC data that is specific to the first user data;

wherein the first configuration is different than the second configuration;

wherein the at least one group of overhead data memory cells of the second block of the plurality of individually erasable blocks of memory cells comprises a different storage capacity than the at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of the plurality of individually erasable blocks of memory cells;

wherein the controller being configured to configure the second block of the plurality of individually erasable blocks of memory cells in the second configuration comprises the controller being configured to reconfigure the second block of the plurality of individually erasable blocks of memory cells to the second configuration from a third configuration comprising the one or more groups of user data memory cells of the second configuration and the at least one group of overhead data memory cells of the second configuration to store second user data;

wherein the controller being configured to configure the first block of the plurality of individually erasable blocks of memory cells in the first configuration comprises the controller being configured to reconfigure the first block to the first configuration from a fourth configuration comprising a group of overhead data memory cells to store all ECC data specific to the second user data; and

wherein while the second block of the plurality of individually erasable blocks of memory cells is in the third configuration and the first block of the plurality of individually erasable blocks of memory cells is in the fourth configuration, a third block of the plurality of individually erasable blocks of memory cells is to store third user data and an other group of overhead data memory cells of the first block of the plurality of individually erasable blocks of memory cells is to store all ECC data specific to the third user data.

18. The memory device of claim 17 , wherein the other group of overhead data memory cells of the first block of the plurality of individually erasable blocks of memory cells that is to store all the ECC data specific to the third user data comprises a larger portion of the first block of the plurality of individually erasable blocks of memory cells than the group of overhead data memory cells to store all the ECC data specific to the second user data when the third user data has a higher reliability than the second user data.

19. The memory device of claim 17 , wherein the controller is configured to determine a space requirement for the ECC data specific to the first user data, the ECC data specific to the second user data, and the ECC data specific to the third user data.

20. The memory device of claim 17 , wherein the first user data has a different space requirement than the second user data, and wherein the ECC data that is specific to the first user data has a different space requirement than the ECC data that is specific to the second user data.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 13208802 · Aug 12, 2011
Related Publication 20150033096A1 · Jan 29, 2015