Frequency synthesis for memory input-output operations
A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
1. An apparatus comprising:
a memory array;
an input/output (I/O) lane coupled to the memory array, wherein the I/O lane is configured to provide data signals to and from the memory array; and
a first clock circuit coupled to the I/O lane, wherein the first clock circuit is configured to provide a first internal clock signal to the I/O lane, wherein the first clock circuit is further configured to synthesize the first internal clock signal based, at least in part, on the data signals provided to the I/O lane.
2. The apparatus of claim 1 , wherein the data signals comprise an encoded I/O scheme.
3. The apparatus of claim 2 , wherein the encoded I/O scheme includes encoded timing information, and wherein the first clock circuit is further configured to extract the encoded timing information to synthesize the first internal clock signal based, at least in part, on the encoded timing information.
4. The apparatus of claim 1 , further comprising a command/address (CA) lane coupled to the first clock circuit, wherein the CA lane is configured to receive memory commands and addresses.
5. The apparatus of claim 1 , further comprising:
a CA lane configured to receive memory commands and addresses; and
a second clock circuit coupled to the CA lane, wherein the second clock circuit is configured to provide a second internal clock signal to the CA lane, wherein the second clock circuit is further configured to synthesize the second internal clock signal based, at least in part, on the memory commands and addresses received by the I/O lane.
6. The apparatus of claim 5 , wherein the second internal clock signal is synthesized independently of the first internal clock signal.
7. The apparatus of claim 5 , wherein the second internal clock signal and the first internal clock signal have a same frequency and different phases.
8. The apparatus of claim 1 , wherein the frequency of the first internal clock signal is based, at least in part, on an external clock signal received by the first clock circuit.
9. The apparatus of claim 1 , wherein the I/O lane comprises two signal lines, wherein the two signal lines are configured to provide the data signals comprising two or more logic levels.
10. The apparatus of claim 1 , wherein the I/O lane comprises three signal lines, wherein the three signal lines are configured to provide the data signals comprising three or more logic levels.
11. An apparatus comprising:
a first memory array;
a first plurality of input/output (I/O) lanes coupled to the first memory array, wherein the first plurality of I/O lanes is configured to send and receive data using an encoded I/O scheme;
a second memory array;
a second plurality of I/O lanes coupled to the second memory array, wherein the second plurality of I/O lanes is configured to send and receive data using the encoded I/O scheme;
a command decoder;
a command/address (CA) lane coupled to the command decoder, wherein the CA lane is configured to receive commands and addresses using the encoded I/O scheme and provide the commands and addresses to the command decoder; and
a clock circuit coupled to the first and second plurality of I/O lanes and the CA lane, wherein the clock circuit is configured to synthesize internal clock signals and provide the internal clock signals to the first and second plurality of I/O lanes and the CA lane,
wherein the internal clock signals are synthesized based, at least in part, on the encoded I/O scheme.
12. The apparatus of claim 11 , wherein the clock circuit comprises:
a plurality of phase aligning loops configured to align phases of the internal clock signals to phases of the data using the encoded I/O scheme; and
a frequency locking loop configured to synthesize at least one of the internal clock signals with a desired frequency and provide the internal clock signal to at least one of the plurality of the phase aligning loops.
13. The apparatus of claim 12 , wherein the plurality of phase aligning loops further comprises a first plurality of phase aligning loops coupled to the first plurality of I/O lanes and the CA lane and a second plurality of phase aligning loops coupled to the second plurality of I/O lanes and the CA lane, wherein the first and second pluralities of phase aligning loops are configured to independently align the phases of the internal clock signals provided to the first and second plurality of I/O lanes and the CA lane.
14. The apparatus of claim 13 , wherein the frequency locking loop further comprises:
a first frequency locking loop coupled to the first plurality of phase aligning loops coupled to the first plurality of I/O lanes;
a second frequency locking loop coupled to the second plurality of phase aligning loops coupled to the second plurality of I/O lanes; and
a third frequency locking loop coupled to the phase aligning loop coupled to the CA lane.
15. The apparatus of claim 12 , wherein the frequency locking loop is configured to synthesize the internal dock signals based, at least in part, on a frequency of an external clock signal.
16. The apparatus of claim 12 , wherein at least one of the plurality of phase aligning loops comprises:
a phase detector configured to detect a phase of the data using the encoded I/O scheme and compare the phase of the data to a phase of an internal clock signal;
a filter circuit configured to receive a result of the comparison of the phase of the data to a phase of the internal clock signal received from the phase detector and generate a filtered signal based, at least in part, on the result;
a phase interpolator configured to receive the filtered signal and the internal clock signal and adjust the phase of the internal clock signal based, at least in part, on the filtered signal; and
a clock distribution network configured to receive the internal clock signal from the phase interpolator and provide the internal clock signal to the phase detector, the internal clock signal provided by the clock distribution network to the phase detector having a propagation delay relative to the internal clock signal received.
17. The apparatus of claim 16 , wherein the filter circuit is a digital filter circuit.
18. The apparatus of claim 12 , wherein the frequency locking loop comprises:
a phase and frequency detector configured to detect a phase and a frequency of an external clock signal and compare the phase and the frequency of the external clock signal to a phase and a frequency of an internal clock signal;
a filter circuit configured to receive a result of the comparison of the external clock signal and the internal clock signal received from the phase and frequency detector and generate a filtered signal based, at least in part, on the result;
a voltage controlled oscillator configured to synthesize the internal clock signal based, at least in part, on the filtered signal; and
a level shifter configured to shift logic levels of the internal clock signal, provide the internal clock signal to the phase and frequency detector, and provide the internal clock signal to at least one of the plurality of phase aligning loops.
19. The apparatus of claim 18 , further comprising a state register coupled to the filter circuit and the voltage controlled oscillator, wherein the state register is configured to store an operating parameter of the frequency locking loop.
20. The apparatus of claim 18 , further comprising a mode register coupled to the frequency locking loop, wherein the mode register is configured to provide a mode control signal to the frequency locking loop.
21. The apparatus of claim 20 , wherein the mode control signal indicates a desired frequency of the internal clock signal.
22. The apparatus of claim 20 , wherein the mode control signal indicates a filtering parameter of the filter circuit.
23. The apparatus of claim 18 , further comprising a frequency divider configured to receive the internal clock signal from the level shifter, divide a frequency of the internal clock signal, and provide a divided frequency signal to the phase and frequency detector.
24. A method comprising:
synthesizing an internal clock signal with a voltage controlled oscillator;
receiving an encoded data signal from a lane of a memory channel;
detecting a phase of the encoded data signal;
comparing the phase of the encoded data signal to a phase of the internal clock signal;
adjusting the phase of the internal clock signal based, at least in part; on the comparison of the phases of the encoded data signal and the internal clock signal; and
providing the internal clock signal to the lane.
25. The method of claim 24 , further comprising receiving an external clock signal and adjusting a frequency of the internal clock signal based at least in part on a frequency of the external clock signal.
26. The method of claim 25 , wherein the frequency of the internal clock signal is higher than the frequency of the external clock signal.
27. The method of claim 24 , further comprising executing operations of the memory channel based, at least in part, on the internal clock signal.
28. The method of claim 24 , wherein the lane of the memory channel is an input/output (I/O) lane.
29. The method of claim 24 , wherein the lane of the memory channel is a command/address (CA) lane.
30. A method comprising:
receiving an input/output (I/O) frequency at a mode register of a memory channel;
synthesizing an internal clock signal with a frequency based on the I/O frequency;
providing the internal clock signal to an I/O lane of the memory channel;
receiving a command on a command/address (CA) lane of the memory channel to enter a write training mode;
receiving a write training pattern on the I/O lane to write to a memory array of the memory channel;
receiving a command on the CA lane to drive a read pattern on the I/O lane from the memory array;
driving the read pattern on the I/O lane from the memory array; and
receiving a command on the CA lane to cease driving the read pattern.
31. The method of claim 30 , further comprising:
powering up the memory channel in a low-speed mode;
receiving a CA training frequency at the mode register;
synthesizing a CA internal clock signal with a frequency based on the CA training frequency;
providing the CA internal clock signal to the CA lane;
receiving a command to enter a CA training mode on the CA lane; and
receiving a training pattern on the CA lane.
32. The method of claim 31 , further comprising operating the memory channel in full-speed mode after receiving the training pattern on the CA lane.
33. The method of claim 31 , further comprising:
receiving a CA operating frequency at the mode register after receiving the training pattern on the CA lane;
synthesizing the CA internal clock signal with a frequency based on the CA operating frequency; and
providing the CA internal clock signal to the CA lane.
34. The method of claim 30 , wherein the method is repeated at regular intervals.
35. The method of claim 30 , wherein the read pattern is configured to calibrate a host coupled to the memory channel.
36. The method of claim 30 , wherein the write training pattern is configured to calibrate a clock circuit of the memory channel, and wherein the clock circuit is configured to synthesize the internal clock signal.
37. The method of claim 30 , wherein the write training pattern is received for a defined period of time.
38. The method of claim 30 , wherein the write training pattern is received until the memory channel provides a lock signal to a memory controller.