IP Library Granted Patent US 9,607,933
Granted Patent B2
US 9,607,933 · App. 14/176,022 · Granted Mar 28, 2017

Lead frame structure for quad flat no-lead package, quad flat no-lead package and method for forming the lead frame structure

Inventor: Diann Fang Lin (Miaoli County, TW)
Assignee: DAWNING LEADING TECHNOLOGY INC.
H01L23/49541H01L21/4828H01L21/4842H01L23/3107H01L23/49548H01L23/49582H01L2224/32245H01L2224/48091H01L2224/48247H01L2224/48257H01L2224/73265H01L2924/181Y10T29/49204
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Quick Facts
Patent No.
US 9,607,933
App. No.
14/176,022
Granted
Mar 28, 2017
Kind
B2
Abstract

A lead frame structure for quad flat no-lead (QFN) package includes a main base, a plurality of terminals and a first metal layer. The main base has a center area for carrying a semiconductor die, and a periphery area surrounding the center area. The plurality of terminals are arranged around the main base. The first metal layer has a first part formed on the periphery area of the main base, and a second part formed on the plurality of terminals. Wherein the main base and the plurality of terminals are formed by a stamping process, and the first metal layer is formed by a plating process before the stamping process.

Claims (22)

1. A lead frame structure for quad flat no-lead (QFN) package, comprising:

a main base, having a center area for carrying a semiconductor die, and a periphery area surrounding the center area;

a plurality of terminals arranged around the main base; and

a first metal layer, having a first part formed on the periphery area of the main base, and a second part formed on the plurality of terminals, wherein the first part of the first metal layer is firmly fixed on a front surface of the main base and the second part of the first metal layer is firmly fixed on front surfaces of the plurality of terminals;

wherein the main base and the terminals are formed by a stamping process, and the first metal layer is formed by a plating process before the stamping process, wherein before the main base and the terminals are formed, a rear surface of the metal base and the terminals are half etched to reduce a thickness of said metal base at an opposite side where the area of the first metal layer is formed, wherein the lead frame structure further comprises another metal layer for covering a rear surface of the main base and covering rear surfaces and side walls of the plurality of terminals.

2. A lead frame structure for quad flat no-lead (QFN) package, comprising:

a main base, having a center area for carrying a semiconductor die, and a periphery area surrounding the center area;

a plurality of terminals arranged around the main base; and

a first metal layer, having a first part formed on the periphery area of the main base, and a second part formed on the plurality of terminals, wherein the first part of the first metal layer is firmly fixed on a front surface of the main base and the second part of the first metal layer is firmly fixed on front surfaces of the plurality of terminals;

wherein the main base and the terminals are formed by a stamping process, and the first metal layer is formed by a plating process before the stamping process, wherein before the main base and the terminals are formed, a rear surface of the metal base and the terminals are half etched to reduce a thickness of said metal base at an opposite side where the area of the first metal layer is formed, wherein the lead frame structure further comprises a plurality of pillars, formed higher than the main base and the plurality of terminals, for supporting a package mold so as to enable package material to be filled to encapsulate the semiconductor die after the package mold is placed on the pillars, wherein the main base and the plurality of terminals are held on a same plane, wherein the lead frame structure further comprises another metal layer for covering a rear surface of the main base and covering rear surfaces and side walls of the plurality of terminals.

3. A quad flat no-lead (QFN) package, comprising:

a lead frame structure, comprising a metal plate and a first metal layer plated thereon, wherein the metal plate with the metal layer thereon is stamped in such a manner that the metal plate forms a main base and a periphery area surrounding the main base to form a plurality of terminals around the main base, wherein before the metal plate with the metal layer thereon is stamped, a rear surface of the metal plate is half etched to reduce a thickness of the metal layer at an opposite side where the area of the first metal layer is formed, wherein the metal layer forms a first part formed on the periphery area of the main base, and a second part formed on the terminals, wherein the first part of the first metal layer is firmly fixed on a front surface of the main base and the second part of the first metal layer is firmly fixed on front surfaces of the terminals;

a semiconductor die, bonded on a center area of the main base, and electrically connected to the first part of the first metal layer and the second part of the first metal layer; and

a package unit, for encapsulating the semiconductor die, wherein the lead frame structure further comprises a plurality of pillars, formed higher than the main base and the plurality of terminals, for supporting a package mold.

4. A quad flat no-lead (QFN) package, comprising:

a lead frame structure, comprising a metal plate and a first metal layer plated thereon, wherein the metal plate with the metal layer thereon is stamped in such a manner that the metal plate forms a main base and a periphery area surrounding the main base to form a plurality of terminals around the main base, wherein before the metal plate with the metal layer thereon is stamped, a rear surface of the metal plate is half etched to reduce a thickness of the metal layer at an opposite side where the area of the first metal layer is formed, wherein the metal layer forms a first part formed on the periphery area of the main base, and a second part formed on the terminals, wherein the first part of the first metal layer is firmly fixed on a front surface of the main base and the second part of the first metal layer is firmly fixed on front surfaces of the terminals;

a semiconductor die, bonded on a center area of the main base, and electrically connected to the first part of the first metal layer and the second part of the first metal layer; and

a package unit, for encapsulating the semiconductor die, wherein the lead frame structure further comprises another metal layer for covering a rear surface of the main base and covering rear surfaces and side walls of the plurality of terminals.

5. A quad flat no-lead (QFN) package, comprising:

a lead frame structure, comprising a metal plate and a first metal layer plated thereon, wherein the metal plate with the metal layer thereon is stamped in such a manner that the metal plate forms a main base and a periphery area surrounding the main base to form a plurality of terminals around the main base, wherein before the metal plate with the metal layer thereon is stamped, a rear surface of the metal plate is half etched to reduce a thickness of the metal layer at an opposite side where the area of the first metal layer is formed, wherein the metal layer forms a first part formed on the periphery area of the main base, and a second part formed on the terminals, wherein the first part of the first metal layer is firmly fixed on a front surface of the main base and the second part of the first metal layer is firmly fixed on front surfaces of the terminals;

a semiconductor die, bonded on a center area of the main base, and electrically connected to the first part of the first metal layer and the second part of the first metal layer; and

a package unit, for encapsulating the semiconductor die, wherein the lead frame structure further comprises a plurality of pillars, formed higher than the main base and the plurality of terminals, for supporting a package mold, wherein the main base and the plurality of terminals are held on a same plane, wherein the lead frame structure further comprises another metal layer for covering a rear surface of the main base and covering rear surfaces and side walls of the plurality of terminals.

Assignments (2)
MERGER Recorded Mar 11, 2019
From: DAWNING LEADING TECHNOLOGY INC.
To: KING YUAN ELECTRONICS CO., LTD.
Reel/Frame 048567/0463 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2014
From: LIN, DIANN FANG
To: DAWNING LEADING TECHNOLOGY INC
Reel/Frame 032177/0453 →
Continuity (1)
Related Publication 20150228561A1 · Aug 13, 2015