IP Library › Granted Patent US 9,607,941
Granted Patent B2
US 9,607,941 · App. 14/669,527 · Granted Mar 28, 2017

Conductive via structure and fabrication method thereof

Inventors: Yan-Heng Chen (Taichung, TW); Chun-Tang Lin (Taichung, TW); Chieh-Yuan Chi (Taichung, TW); Mu-Hsuan Chan (Taichung, TW)
Assignee: Siliconware Precision Industries Co., Ltd.
H01L23/5226H01L21/76802H01L21/76879H01L23/3107H01L23/49822H01L23/49827H01L23/5389H01L23/53228H01L21/76831H01L23/3114H01L2924/0002
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Quick Facts
Patent No.
US 9,607,941
App. No.
14/669,527
Granted
Mar 28, 2017
Kind
B2
Abstract

A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.

Claims (23)

1. A conductive via structure, comprising:

an encapsulant having a plurality of openings penetrating therethrough;

a dielectric layer formed on the encapsulant and filled in the openings of the encapsulant, wherein a plurality of vias are formed in the dielectric layer in the openings of the encapsulant and have even wall surfaces, and the dielectric layer is made of a photosensitive material; and

a conductive material filled in the vias.

2. The structure of claim 1 , wherein the openings of the encapsulant have uneven wall surfaces.

3. The structure of claim 1 , wherein the wall surfaces of the openings have an average roughness of 2 to 60 um.

4. The structure of claim 1 , wherein the openings have a maximum width of 40 to 400 um.

5. The structure of claim 1 , wherein the dielectric layer in the openings of the encapsulant has a thickness of 30 to 50 um.

6. The structure of claim 1 , wherein the vias have a maximum width of 30 to 350 um.

7. The structure of claim 1 , wherein the conductive material is copper.

8. The structure of claim 1 , wherein the vias are completely filled with the conductive material.

9. A method for fabricating a conductive via structure, comprising the steps of:

forming in an encapsulant a plurality of openings penetrating therethrough;

forming a dielectric layer made of a photosensitive material on the encapsulant and in the openings of the encapsulant;

forming a plurality of vias in the dielectric layer in the openings of the encapsulant by exposure, wherein the vias have even wall surfaces; and

forming a conductive material in the vias.

10. The method of claim 9 , wherein the openings of the encapsulant are formed by laser drilling.

11. The method of claim 9 , wherein wall surfaces of the openings have an average roughness of 2 to 60 um.

12. The method of claim 9 , wherein the openings have a maximum width of 40 to 400 um.

13. The method of claim 9 , wherein the dielectric layer in the openings of the encapsulant has a thickness of 30 to 50 um.

14. The method of claim 9 , wherein the vias have a maximum width of 30 to 350 um.

15. The method of claim 9 , wherein the conductive material is copper.

16. The method of claim 9 , wherein the conductive material is formed by electroplating.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2015
From: CHEN, YAN-HENG; LIN, CHUN-TANG; CHI, CHIEH-YUAN; CHAN, MU-HSUAN
To: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Reel/Frame 035264/0139 →
Priority Claims (1)
TW 103113640 A · Apr 15, 2014 · national
Continuity (1)
Related Publication 20150294938A1 · Oct 15, 2015