Semiconductor chip, semiconductor package and fabricating method thereof
Provided are a semiconductor chip, a semiconductor package and a fabricating method thereof, which can reduce or prevent cracks from being generated or propagated due to an external pressure. The semiconductor chip includes a semiconductor substrate including a first region and a second region, a plurality of interlayer insulation layers formed on the semiconductor substrate, a first crack stopper formed in the plurality of interlayer insulation layers of the first region, an interconnector formed in the plurality of interlayer insulation layers of the second region, a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, a bonding pad on the plurality of interlayer insulation layers of the first region, electrically connected to the pad wire, and a protection layer covering the pad wire and exposing the bonding pad. The first crack stopper is positioned at a lower level than the bonding pad and is formed to completely surround the bonding pad while not overlapping with the bonding pad and not being connected to the pad wire.
1. A semiconductor chip comprising:
a semiconductor substrate including a first region and a second region;
a plurality of interlayer insulation layers formed on the semiconductor substrate;
a first crack stopper formed in the plurality of interlayer insulation layers of the first region;
an interconnector formed in the plurality of interlayer insulation layers of the second region;
a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, and a bonding pad formed on the plurality of interlayer insulation layers of the first region, electrically connected to the pad wire; and
a protection layer covering on the pad wire and exposing the bonding pad,
wherein the first crack stopper is positioned at a lower level than the bonding pad and is formed to completely surround the bonding pad in a plan view while not overlapping with the bonding pad and not being directly connected to the pad wire, and
wherein the first crack stopper further comprises:
a main part not overlapping with the bonding pad and completely surrounding the bonding pad in a plan view; and
a protruding part horizontally extending to the bonding pad and having at least a portion overlapping with the bonding pad.
2. The semiconductor chip of claim 1 , wherein the first crack stopper includes a plurality of conductive layers.
3. The semiconductor chip of claim 2 , wherein the first crack stopper further includes at least one via connecting the conductive layers.
4. The semiconductor chip of claim 2 , wherein the first crack stopper further includes a gate connected to the conductive layers and formed on the semiconductor substrate.
5. The semiconductor chip of claim 4 , wherein the first crack stopper further includes a contact connecting the gate and the conductive layers.
6. The semiconductor chip of claim 4 , further comprising a trench isolation layer formed in the semiconductor substrate under the gate and overlapping with the gate.
7. The semiconductor chip of claim 1 , wherein the plurality of interlayer insulation layers include a low-k dielectric.
8. The semiconductor chip of claim 1 , wherein the first crack stopper includes a plurality of loop-type structures completely surrounding the bonding pad in a plan view.
9. The semiconductor chip of claim 1 , further comprising a second crack stopper disposed under the bonding pad and having at least a portion overlapping with the bonding pad.
10. A semiconductor chip comprising:
a semiconductor substrate including a first region and a second region;
a trench isolation layer formed in the semiconductor substrate of the first region;
a gate formed on the trench isolation layer of the first region;
a plurality of interlayer insulation layers stacked on the semiconductor substrate of the first region and the second region;
a pad wire disposed on the plurality of interlayer insulation layers of the first region and the second region;
a bonding pad formed on the plurality of interlayer insulation layers of the first region and connected to the pad wire;
a crack stopper including the gate and a plurality of conductive layers stacked in the plurality of interlayer insulation layers of the first region; and
an interconnector including a plurality of wire conductive layers disposed in the plurality of interlayer insulation layers of the second region and connected to the pad wire,
wherein the crack stopper is positioned at a lower level than the bonding pad and completely surrounds the bonding pad in a plan view, and wherein each of the conductive layers of the crack stopper includes a first part completely surrounding the bonding pad in a plan view, and a second part horizontally extending from the first part and partially overlapping with the bonding pad.
11. The semiconductor chip of claim 10 , wherein the crack stopper further comprises one or more vias connecting the conductive layers.
12. The semiconductor chip of claim 10 , further comprising a contact connecting the gate and the conductive layers.
13. The semiconductor chip of claim 11 , wherein the conductive layers of the crack stopper include a first structure and a second structure.
14. The semiconductor chip of claim 13 , wherein the first structure completely surrounds the bonding pad in a plan view while not overlapping with the bonding pad, and
wherein the second structure is partially overlapping with the bonding pad.
15. A semiconductor package comprising:
a package substrate including a substrate pad disposed thereon;
a semiconductor chip mounted on the package substrate and including a bonding pad; and
a wire connecting the substrate pad and the bonding pad,
wherein the semiconductor chip comprises:
a gate on a semiconductor substrate;
a plurality of interlayer insulation layers covering the gate and disposed under the bonding pad; and
a crack stopper comprising a plurality of conductive layers stacked in the interlayer insulation layers and connected to the gate, the conductive layers not being directly connected to the bonding pad and completely surrounding the bonding pad in a plan view,
wherein each of the plurality of conductive layers of the crack stopper comprises a protrusion part overlapping a portion of the bonding pad.
16. The semiconductor package of claim 15 , where the conductive layers are positioned at a lower level than the bonding pad.
17. The semiconductor package of claim 15 , wherein a portion of the conductive layers do not overlap with the boding pad and have loop-type structures.
18. A semiconductor chip comprising:
a semiconductor substrate including a first region and a second region;
a plurality of interlayer insulation layers formed on the semiconductor substrate;
a first crack stopper formed in the plurality of interlayer insulation layers of the first region;
an interconnector formed in the plurality of interlayer insulation layers of the second region;
a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, and a bonding pad formed on the plurality of interlayer insulation layers of the first region, electrically connected to the boding pad; and
a protection layer covering on the pad wire and exposing the bonding pad,
wherein the first crack stopper is positioned at a lower level than the bonding pad and is formed to completely surround the bonding pad in a plan view while not overlapping with the bonding pad and not being directly connected to the pad wire, and wherein the first crack stopper includes a main part not overlapping with the bonding pad and completely surrounding the bonding pad in a plan view and a protruding part horizontally extending to the bonding pad and having at least a portion overlapping with the bonding pad.