Semiconductor device and method of fabricating 3D package with short cycle time and high yield
A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.
1. A method of making a semiconductor device, comprising:
providing a first manufacturing line;
providing a second manufacturing line;
forming a first redistribution interconnect structure using the first manufacturing line;
forming a second redistribution interconnect structure using the second manufacturing line;
testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU);
disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure after determining the first KGU;
testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and
disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD.
2. The method of claim 1 , further including:
providing a third manufacturing line;
testing a semiconductor die of a semiconductor wafer to determine the KGD; and
dicing the KGD from the semiconductor wafer using the third manufacturing line.
3. The method of claim 1 , further including:
testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and
disposing a dummy die over the rejected unit of the first redistribution interconnect structure.
4. The method of claim 1 , wherein forming the second redistribution interconnect structure further includes disposing a discrete passive device over a conductive layer of the second redistribution interconnect structure.
5. The method of claim 1 , wherein a resolution of the second manufacturing line used in forming the second redistribution interconnect structure is greater than a resolution of the first manufacturing line used in forming the first redistribution interconnect structure.
6. The method of claim 1 , further including disposing the second KGU of the second redistribution interconnect structure over the KGD opposite the first KGU of the first redistribution interconnect structure.
7. A method of making a semiconductor device, comprising:
providing a first manufacturing line;
forming a first redistribution interconnect structure using the first manufacturing line;
testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU); and
disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure.
8. The method of claim 7 , further including:
providing a third manufacturing line;
testing a semiconductor die of a semiconductor wafer to determine the KGD; and
dicing the KGD from the semiconductor wafer using the third manufacturing line.
9. The method of claim 7 , further including:
testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and
disposing a dummy die over the rejected unit of the first redistribution interconnect structure.
10. The method of claim 7 , further including forming a second redistribution interconnect structure using a second manufacturing line simultaneously with forming the first redistribution interconnect structure, wherein a resolution of the second manufacturing line is different than a resolution of the first manufacturing line.
11. The method of claim 10 , wherein forming the second redistribution interconnect structure includes using a resolution greater than the resolution of the first manufacturing line.
12. The method of claim 7 , further including disposing a discrete passive device over the first redistribution interconnect structure.
13. The method of claim 7 , further including:
forming a second redistribution interconnect structure using a second manufacturing line;
testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and
disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD.
14. The method of claim 7 , further including:
forming a plurality of conductive pillars over the first redistribution interconnect structure; and
disposing the KGD between the plurality of conductive pillars.
15. A method of making a semiconductor device, comprising:
forming a first redistribution interconnect structure using a first manufacturing line;
forming a second redistribution interconnect structure using a second manufacturing line;
testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and
disposing a dummy die over the rejected unit of the first redistribution interconnect structure.
16. The method of claim 15 , further including:
testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU); and
disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure.
17. The method of claim 16 , further including:
testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and
disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD.
18. The method of claim 17 , further including:
providing a third manufacturing line;
testing a semiconductor die of a semiconductor wafer to determine the KGD; and
dicing the KGD from the semiconductor wafer using the third manufacturing line.
19. The method of claim 15 , wherein forming the second redistribution interconnect structure further includes disposing a discrete passive device over a conductive layer of the second redistribution interconnect structure.
20. The method of claim 15 , wherein a resolution of the second manufacturing line is different than a resolution of the first manufacturing line.
21. The method of claim 20 , wherein forming the second redistribution interconnect structure includes using a resolution greater than the resolution of the first manufacturing line.