IP Library › Granted Patent US 9,659,858
Granted Patent B2
US 9,659,858 · App. 14/801,259 · Granted May 23, 2017

Low-stress vias

Inventors: Ilyas Mohammed (San Jose, CA); Belgacem Haba (Saratoga, CA); Cyprian Emeka Uzoh (San Jose, CA)
Assignee: Tessera, Inc.
H01L23/5226H01L21/76898H01L23/481H01L23/5329H01L23/53223H01L23/53238H01L23/53252H01L2224/10135H01L2924/07811
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Quick Facts
Patent No.
US 9,659,858
App. No.
14/801,259
Granted
May 23, 2017
Kind
B2
Abstract

A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Claims (27)

1. A component, comprising:

a substrate having a front surface and a rear surface remote therefrom, the substrate having a coefficient of thermal expansion (CTE) less than 10 ppm/° C.;

an opening extending from the rear surface towards the front surface, the opening defining an inner surface between the front and rear surfaces; and

an electrically conductive via extending within the opening, the conductive via including a first electrically conductive layer overlying the inner surface and a second electrically conductive region overlying the first conductive layer and electrically coupled to the first conductive layer, the second conductive region having a CTE greater than a CTE of the first conductive layer, the first electrically conductive layer having a thickness at least 10% of a diameter of the conductive via,

wherein the substrate has a transition surface between a portion of the opening and at least one of the front or rear surfaces.

2. The component as claimed in claim 1 , wherein a radius of curvature of the transition surface is greater than 5% of a radius of the electrically conductive via.

3. The component as claimed in claim 1 , wherein the second conductive region has an outer surface facing the first conductive layer and an inner surface surrounding a central opening defined within the second conductive region.

4. The component as claimed in claim 3 , further comprising an insulating dielectric layer coating the inner surface of the second conductive region.

5. The component as claimed in claim 3 , wherein the electrically conductive via has front and rear axial ends, and the central opening is a recess formed at one of the front or rear axial ends.

6. The component as claimed in claim 5 , wherein the central opening is a recess formed at the rear axial end of the electrically conductive via, and the recess extends below the rear surface of the substrate.

7. The component as claimed in claim 6 , wherein an exposed surface of the recess is coated with a barrier layer that is a different material than a material of the electrically conductive via.

8. The component as claimed in claim 6 , wherein an exposed surface of the recess is coated with a polymer that at least partially fills the recess.

9. The component as claimed in claim 6 , wherein the recess has a maximum diameter less than a diameter of the electrically conductive via in a lateral direction parallel to the front surface of the substrate.

10. The component as claimed in claim 1 , wherein the first conductive layer has a Young's modulus greater than a Young's modulus of the second conductive region.

11. The component as claimed in claim 1 , further comprising a barrier layer within the opening, at least a portion of the electrically conductive via being in contact with the barrier layer.

12. The component as claimed in claim 1 , wherein the second conductive region conformally coats the first conductive layer.

13. The component as claimed in claim 1 , wherein the second conductive region extends within the opening between the front and rear surfaces of the substrate.

14. The component as claimed in claim 1 , further comprising a conductive contact having a contact surface exposed at the rear surface for interconnection with an external element.

15. The component as claimed in claim 1 , wherein the substrate consists essentially of semiconductor material, the component further comprising an insulating dielectric layer coating an inner surface of the opening, the dielectric layer separating and insulating the electrically conductive via from the substrate at least within the opening.

16. The component as claimed in claim 1 , wherein an electrically conductive portion of the electrically conductive via directly contacts material of the substrate.

17. The component as claimed in claim 16 , wherein the substrate consists essentially of dielectric material.

18. The component as claimed in claim 1 , further comprising a conductive element at the front surface electrically connected with the electrically conductive via, wherein the substrate embodies a plurality of active semiconductor devices electrically connected with the conductive element.

19. The component as claimed in claim 18 , wherein the conductive element has a top surface facing away from the front surface of the substrate and a bottom surface opposite the front surface, and the electrically conductive via is formed in contact with the bottom surface of the conductive element.

20. The component as claimed in claim 19 , wherein the second conductive region is separated from the conductive element by the first conductive layer.

21. The component as claimed in claim 1 , wherein the electrically conductive via also includes a third conductive layer between the first conductive layer and the inner surface, the third conductive layer comprising a material different than materials of the first conductive layer and the second conductive region.

22. A system comprising the component as claimed in claim 1 and one or more other electronic components electrically connected to the component.

23. The system as claimed in claim 22 , further comprising a housing, the component and the other electronic components being mounted to the housing.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0373 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0816 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2015
From: MOHAMMED, ILYAS; HABA, BELGACEM; UZOH, CYPRIAN EMEKA
To: TESSERA, INC.
Reel/Frame 036123/0580 →
Continuity (3)
Continuation 14450109 · Aug 1, 2014
Division 13193814 · Jul 29, 2011
Related Publication 20150325498A1 · Nov 12, 2015