Lateral/vertical semiconductor device

1. A method, comprising:

designing a lateral semiconductor device comprising:

a device channel formed of a group III-nitride material;

a first contact on a first end of the device channel;

a second contact on a second end of the device channel, wherein the second end is opposite the first end, and wherein the first and second contacts are located on a first side of the device channel;

a space-charge generating layer formed of a group III-nitride material located on a second side of the device channel opposite the first side; and

an electrode electrically connected to the space-charge generating layer and located on an opposite side of the space-charge generating layer as the device channel, wherein the designing includes selecting a set of attributes for the space-charge generating layer such that the space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the first contact and the second contact; and

fabricating the lateral semiconductor device according to the design.

2. The method of claim 1 , wherein the device is a field effect transistor, the device further including a gate contact to the device channel located on the first side of the device channel between the first contact and the second contact.

3. A lateral semiconductor device, comprising:

a device channel;

a first contact on a first end of the device channel;

a second contact on a second end of the device channel, wherein the second end is opposite the first end, and wherein the first and second contacts are located on a first side of the device channel;

a space-charge generating layer located on a second side of the device channel opposite the first side; and

an electrode electrically connected to the space-charge generating layer and located on an opposite side of the space-charge generating layer as the device channel, wherein the space-charge generating layer has a set of attributes configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the first contact and the second contact;

wherein the device channel and the space-charge generating layer are formed of group III-nitride materials.

4. The device of claim 3 , wherein the electrode includes an edge profile with rounded corners.

5. The device of claim 3 , wherein the device is a field effect transistor, the device further including a gate contact to the device channel located on the first side of the device channel between the first contact and the second contact, wherein the first contact includes a source contact and the second contact includes a drain contact.

6. The device of claim 5 , further comprising a low conducting electrode formed between the gate contact and the drain contact.

7. The device of claim 5 , wherein the gate contact includes a plurality of instances of the gate contact forming islands of the gate contact, each extending in a direction perpendicular to the source contact and the drain contact.

8. The device of claim 7 , wherein each of the gate contact islands includes an edge profile with rounded corners.

9. The device of claim 5 , wherein the electrode includes a first electrode section that contacts a bottom surface of the space-charge generating layer, a second electrode section that contacts a side surface of the space-charge generating layer, and a third electrode section that contacts the second contact.

10. The device of claim 9 , wherein the first electrode section extends from one side surface of the space-charge generating layer along the bottom surface of the space-charge generating layer towards an opposing side surface of the space-charge generating layer, wherein the first electrode section extends under a portion of the gate contact.

11. The device of claim 9 , wherein the first electrode section, the second electrode section, and the third electrode section form a smooth, bent shape.

12. The device of claim 9 , wherein the first electrode section, the second electrode section, and the third electrode section form an L-shape.

13. A circuit, comprising:

a lateral semiconductor device comprising:

a device channel;

a first contact on a first end of the device channel;

a second contact on a second end of the device channel, wherein the second end is opposite the first end, and wherein the first and second contacts are located on a first side of the device channel;

a space-charge generating layer located on a second side of the device channel opposite the first side; and

an electrode electrically connected to the space-charge generating layer and located on an opposite side of the space-charge generating layer as the device channel;

an input circuit electrically connected to the first contact; and

an output circuit electrically connected to the second contact, wherein the space-charge generating layer has a set of attributes configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the first contact and the second contact;

wherein the device channel and the space-charge generating layer are formed of group III-nitride materials.

14. The circuit of claim 13 , wherein the device is a field effect transistor, the device further including a gate contact to the device channel located on the first side of the device channel between the first contact and the second contact, wherein the first contact includes a source contact and the second contact includes a drain contact, and the circuit further includes one or more field-control electrodes connected to a gate-drain region formed between the gate contact and the drain contact.

15. The circuit of claim 14 , further comprising a voltage source coupled to the one or more field-control electrodes.

16. The circuit of claim 14 , wherein the one or more field-control electrodes are formed over a surface side of the device channel.

17. The circuit of claim 14 , further comprising a dielectric layer formed between the gate contact and the drain contact, wherein the one or more field-control electrodes are formed on the dielectric layer.

18. The circuit of claim 14 , further comprising a second set of electrodes extending into the space-charge generating layer from the electrode located on an opposite side of the space-charge generating layer as the device channel.

19. The circuit of claim 18 , wherein the second set of electrodes comprise field-control electrodes for controlling a field distribution of the device channel of the field effect transistor.

20. The circuit of claim 19 , further comprising a dielectric layer located between the device channel and the second set of electrodes.