IP Library Granted Patent US 9,660,040
Granted Patent B2
US 9,660,040 · App. 14/926,657 · Granted May 23, 2017

Transistor contacts self-aligned two dimensions

Inventors: Andy Chih-Hung Wei (Queensbury, NY); Guillaume Bouche (Malta, NY); Mark A. Zaleski (Malta, NY); Tuhin Guha Neogi (Hopewell Junction, NY); Jason E. Stephens (Hopewell Junction, NY); Jongwook Kye (Sunnyvale, CA); Jia Zeng (Sunnyvale, CA)
Assignee: GLOBALFOUNDRIES INC.
H01L29/41758H01L21/0217H01L21/02164H01L21/28568H01L21/76834H01L21/76895H01L21/76897H01L21/823475H01L21/823871H01L21/823878H01L23/5329H01L23/53228H01L23/53257H01L27/088H01L27/092H01L29/41725H01L29/66462H01L29/78H01L2924/0002
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Quick Facts
Patent No.
US 9,660,040
App. No.
14/926,657
Granted
May 23, 2017
Kind
B2
Abstract

Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Claims (11)

1. A semiconductor structure comprising:

a plurality of transistor gates;

a plurality of transistor source/drain contact areas;

a first capping layer disposed on a subset of the plurality of transistor gates;

a second capping layer disposed on a subset of the plurality of transistor source/drain contact areas; and

a metallization layer disposed on the first capping layer and second capping layer.

2. The semiconductor structure of claim 1 , wherein the metallization layer is in electrical contact with at least one transistor gate of the plurality of transistor gates.

3. The semiconductor structure of claim 1 , wherein the metallization layer is in electrical contact with at least one source/drain contact area of the plurality of transistor source/drain contact areas.

4. The semiconductor structure of claim 1 , further comprising a dielectric region bounding the metallization layer.

5. The semiconductor structure of claim 4 , further comprising a plurality of spacers adjacent to each transistor gate of the plurality of transistor gates.

6. The semiconductor structure of claim 5 , wherein the first capping layer is comprised of silicon nitride, the second capping layer is comprised of silicon oxide, the dielectric region is comprised of silicon oxycarbide, and the plurality of spacers are comprised of a material selected from the group consisting of silicon oxycarbide and silicon oxycarbonitride.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2015
From: WEI, ANDY CHIH-HUNG; BOUCHE, GUILLAUME; ZALESKI, MARK A.; NEOGI, TUHIN GUHA; STEPHENS, JASON E.; KYE, JONGWOOK; ZENG, JIA
To: GLOBALFOUNDRIES INC.
Reel/Frame 036917/0082 →
Continuity (2)
Continuation 14246476 · Apr 7, 2014
Related Publication 20160049481A1 · Feb 18, 2016