Substrate for semiconductor package and semiconductor package having the same

1. A semiconductor package, comprising:

a substrate including:

a core layer having a first surface and a second surface which is opposite to the first surface,

a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer exposed from the core layer and a second electrode disposed over the first surface, and

a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed;

a first semiconductor chip disposed over the first surface of the core layer;

a second semiconductor chip stacked over the first semiconductor chip;

a first connection member for coupling the first semiconductor chip with the first electrode; and

a second connection member for coupling the second semiconductor chip with the second electrode.

2. The semiconductor package of claim 1 ,

wherein the core layer including the wiring layer includes a first core layer,

wherein the core layer including the wiring layer includes a second core layer formed over the first core layer,

wherein the wiring layer includes a first wiring layer formed over a lower surface of the first core layer,

wherein the wiring layer includes a second wiring layer formed between the first core layer and the second core layer, and

wherein the wiring layer includes a third wiring layer formed over an upper surface of the second core layer.

3. The semiconductor package of claim 1 , wherein the core layer including the wiring layer includes:

a first core layer;

a second core layer formed over the first core layer; and

a third core layer formed over the second core layer.

4. The semiconductor package of claim 1 , wherein the first and second connection members are conductive wires.

5. The semiconductor package of claim 1 , further comprising spacers interposed between the substrate and the first semiconductor chip and between the first semiconductor chip and the second semiconductor chip.

6. The semiconductor package of claim 2 , wherein the wiring layer further includes:

a first via pattern connecting the first wiring layer with the second wiring layer; and

a second via pattern connecting the second wiring layer with the third wiring layer.

7. The semiconductor package of claim 2 ,

wherein the wiring layer includes a first wiring layer formed over a lower surface of the first core layer; and

wherein the semiconductor package further comprises external connection electrodes formed in portions of the first wiring layer.

8. The semiconductor package of claim 3 ,

wherein the wiring layer includes a first wiring layer formed over a lower surface of the first core layer,

wherein the wiring layer includes a second wiring layer formed between the first core layer and the second layer,

wherein the wiring layer includes a third wiring layer formed between the second core layer and the third core layer,

wherein the wiring layer includes a fourth wiring layer formed over an upper surface of the third core layer,

wherein the wiring layer further includes a first via pattern connecting the first wiring layer with the second wiring layer,

wherein the wiring layer further includes a second via pattern connecting the second wiring layer with the third wiring layer, and

wherein the wiring layer further includes a third via pattern connecting the third wiring layer with the fourth wiring layer.

9. The semiconductor package of claim 8 , further comprising a third electrode disposed over the third core layer.