Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication
Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.
1. A method comprising:
recessing a semiconductor material to form a cavity therein adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and
implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface comprising, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure.
2. The method of claim 1 , wherein implanting the one or more dopants into the semiconductor material through the first cavity surface positions, at least in part, the interface of the implanted region parallel to the second cavity surface of the cavity.
3. The method of claim 1 , wherein implanting the one or more dopants comprises implanting the one or more dopants through the first cavity surface at an implant angle which extends the interface of the implanted region within the semiconductor material at an angle from the second cavity surface of the cavity.
4. The method of claim 1 , wherein the extended channel interface further comprises, in part, the second cavity surface of the cavity.
5. The method of claim 4 , wherein the interface of the implanted region to the channel region is non-planar with the second cavity surface of the cavity.
6. The method of claim 1 , wherein the implanting comprises implanting the one or more dopants through the first cavity surface while minimizing lateral diffusion of the one or more dopants within the semiconductor material, thereby controlling location of the interface of the implanted region within the semiconductor material to the channel region.
7. The method of claim 6 , wherein the implanting comprises implanting the one or more dopants into the semiconductor material through the first cavity surface at an implant angle which is normal to the first cavity surface, the implant angle facilitating forming the interface of the implanted region to the channel region coplanar with the second cavity surface.
8. The method of claim 6 , wherein the implanting comprises implanting the one or more dopants into the semiconductor material through the first cavity surface with an implant energy which defines a depth of the interface of the implanted region to the channel region at a desired depth within the semiconductor material.
9. The method of claim 1 , further comprising forming a source region or a drain region within, at least partially, the cavity subsequent to the implanting of the one or more dopants through the first cavity surface, wherein the forming comprises epitaxially growing the source region or the drain region at least partially within the cavity, wherein the implanting and the epitaxially growing together define the extended channel interface to the channel region of the semiconductor structure.
10. The method of claim 1 , wherein the implanting the one or more dopants to define the implanted region within the semiconductor material facilitates increasing junction on-current while minimizing junction leakage current of the semiconductor structure.
11. The method of claim 1 , wherein the cavity comprises a source cavity and the implanted region comprises an implanted source region, the extended channel interface comprises an extended source channel interface and the recessing further comprises recessing the semiconductor material to also form a drain cavity adjacent to the channel region, and wherein the implanting further comprises implanting through a first drain cavity surface the one or more dopants to form a drain implanted region, and wherein the method further comprises epitaxially growing a source region over the implanted source region and a drain region over the implanted drain region, the implanting and the epitaxially growing defining the extended source channel interface and an extended drain channel interface, at least in part, within the semiconductor material.
12. The method of claim 1 , wherein the implanting further comprises performing an annealing process, subsequent to the implanting of the one or more dopants into the semiconductor material, the annealing process facilitating stabilizing the implanted region within the semiconductor material.
13. The method of claim 1 , wherein the method further comprises fabricating a fin-type field effect transistor (FinFET), the FinFET being the semiconductor structure, and the fabricating including the recessing and the implanting.