Semiconductor device with reduced poly spacing effect

1. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate having a semiconductor layer;

forming a first gate electrode over said semiconductor layer;

forming a second gate electrode over said semiconductor layer and laterally adjacent to said first gate electrode;

forming a mask layer in a space between said laterally adjacent first and second gate electrodes, wherein said mask layer exposes each of said laterally adjacent first and second gate electrodes, covers a first portion of said semiconductor layer in said space between said laterally adjacent first and second gate electrodes, and exposes second portions of said semiconductor layer in said space between said mask layer and each of said laterally adjacent first and second gate electrodes;

etching a cavity into each of said exposed second portions of said semiconductor layer in said space between said laterally adjacent first and second gate electrodes using said mask layer as an etching mask;

forming a semiconductor material in said etched cavities; and

removing said mask layer after forming said semiconductor material.

2. The method of claim 1 , further comprising forming a first P-channel transistor having said first gate electrode and forming a second P-channel transistor having said second gate electrode and forming source/drain regions in said semiconductor material.

3. The method of claim 1 , wherein said semiconductor material is a stress-inducing material comprising one of silicon and a mixture of silicon and germanium and wherein said semiconductor layer comprises silicon.

4. The method of claim 1 , further comprising:

forming a first P-channel transistor comprising said first gate electrode;

forming a second P-channel transistor comprising said second gate electrode;

forming an N-channel transistor comprising a third gate electrode over said semiconductor layer; and

forming said mask layer over said third gate electrode and over regions of said semiconductor layer adjacent to said third gate electrode.

5. The method of claim 1 , wherein said semiconductor substrate is one of an SOI and an FDSOI substrate.

6. The method of claim 1 , wherein said mask layer that is formed between said first and second gate electrodes comprises a lateral width of about 0.8 to 1.2 times a lateral width of one of said first and second gate electrodes.

7. A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of laterally adjacent first gate electrodes of a plurality of respective first P-channel transistors with a first gate electrode spacing over a first region of a semiconductor layer;

forming a plurality of third gate electrodes of a plurality of respective N-channel transistors over a third region of said semiconductor layer;

forming a mask layer, over each of said plurality of third gate electrodes, over portions of said third region of said semiconductor layer adjacent to each of said plurality of third gate electrodes, and in first spaces defined between each of said plurality of laterally adjacent first gate electrodes formed over said first region of said semiconductor layer, wherein said mask layer exposes each of said plurality of laterally adjacent first gate electrodes, covers a first portion of said semiconductor layer positioned in said respective first spaces between each of said plurality of laterally adjacent first gate electrodes, and exposes second portions of said semiconductor layer positioned in said respective first spaces between each of said plurality of laterally adjacent first gate electrodes;

etching first cavities into each of said exposed second portions of said first region of said semiconductor layer in each of said respective first spaces using said mask layer as an etching mask;

filling said first cavities with a first stress-inducing semiconductor material; and

removing said mask layer after forming said first stress-inducing semiconductor material.

8. The method of claim 7 , further comprising:

forming a plurality of laterally adjacent second gate electrodes of a plurality of respective second P-channel transistors with a second gate electrode spacing over a second region of said semiconductor layer, said second gate electrode spacing being smaller than said first gate electrode spacing, wherein second spaces are defined between each of said plurality of laterally adjacent second gate electrodes;

etching second cavities into said second region of said semiconductor layer in said respective second spaces between each of said plurality of laterally adjacent second gate electrodes without using an etching mask positioned in said respective second spaces; and

filling said second cavities with a second stress-inducing semiconductor material.

9. The method of claim 7 , wherein portions of said mask layer formed in said first spaces between said plurality of laterally adjacent first gate electrodes are centered between said respective first gate electrodes.

10. The method of claim 7 , wherein portions of said mask layer formed in said first spaces between said plurality of laterally adjacent first gate electrodes comprise a lateral width of 0.8 to 1.2 times a lateral width of said respective first gate electrodes.

11. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate comprising laterally adjacent gate electrodes formed over a semiconductor layer of said semiconductor substrate;

determining a gate electrode spacing between said laterally adjacent gate electrodes;

if said determined gate electrode spacing exceeds a predetermined threshold, then forming a mask layer in a space defined between said laterally adjacent gate electrodes and forming cavities in said semiconductor layer in said space defined between said gate electrodes using said mask layer an etching mask, wherein said mask layer exposes each of said laterally adjacent gate electrodes and said semiconductor layer positioned in said space between said mask layer and each of said respective laterally adjacent gate electrodes;

if said determined gate electrode spacing does not exceed said predetermined threshold, then forming cavities in said semiconductor layer in said space defined between said laterally adjacent gate electrodes without forming a mask layer in said space between said laterally adjacent gate electrodes;

filling said cavities with a stress-inducing semiconductor material; and

removing said mask layer after forming said stress-inducing semiconductor material.

12. The method of claim 11 , wherein said semiconductor substrate is one of an SOI and an FDSOI substrate, said semiconductor layer comprises silicon and said stress-inducing material comprises one of silicon and a mixture of silicon and germanium.

13. The method of claim 11 , wherein said semiconductor substrate further has additional gate electrodes and wherein said mask layer is formed as part of a masking material layer formed over said additional gate electrodes and over regions of said semiconductor layer adjacent to said additional gate electrodes.

14. The method of claim 11 , wherein said laterally adjacent gate electrodes are formed immediately adjacent one another such that no additional gate electrodes are formed therebetween prior to forming said cavities in said semiconductor layer.

15. A method of manufacturing a semiconductor device having P-channel and N-channel transistors, the method comprising:

forming a plurality of first gate electrodes of a plurality of respective first P-channel transistors with a first gate electrode spacing over a first region of a semiconductor layer;

forming a plurality of second gate electrodes of a plurality of respective second P-channel transistors with a second gate electrode spacing smaller than said first gate electrode spacing over a second region of a semiconductor layer;

forming a mask layer in a first space defined between each of said plurality of first gate electrodes formed over said first region of said semiconductor layer;

etching first cavities into said first region of said semiconductor layer in said first spaces defined between each of said plurality of first gate electrodes using said mask layer formed in each of said respective first spaces as an etching mask;

etching second cavities into said second region of said semiconductor layer in said second spaces defined between each of said plurality of second gate electrodes without using a mask layer positioned in any of said respective second spaces;

filling said first cavities with a first stress-inducing semiconductor material; and

filling said second cavities with a second stress-inducing semiconductor material.

16. The method of claim 1 , wherein said second gate electrode is formed immediately adjacent to said first gate electrode such that no additional gate electrodes are formed in said space therebetween prior to etching said cavities into said exposed second portions of said semiconductor layer.

17. The method of claim 7 , wherein said plurality of laterally adjacent first gate electrodes are formed immediately adjacent one another such that no additional gate electrodes are formed therebetween prior to etching said first cavities into said exposed second portions of said first region of said semiconductor layer.