Methods to form multi threshold-voltage dual channel without channel doping
Methods to form multi V t channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.
1. A method comprising:
providing an interfacial layer along the entirety of and on an upper surface of a semiconductor substrate;
forming conformally a first high-k dielectric layer along the entirety of and on the interfacial layer;
forming conformally a second high-k dielectric layer and a first cap layer, respectively, along the entirety of and on the first high-k dielectric layer while the interfacial layer exists along the entirety of the upper surface of the semiconductor substrate;
removing the second high-k dielectric and first cap layers in first and second regions;
forming a second cap layer on the first high-k dielectric layer in the first and second regions and on the first cap layer in a third region;
performing an annealing process;
removing the second cap layer from all regions and the first cap layer from the third region;
forming a third high-k dielectric layer over all regions;
forming conformally a work-function composition layer and a barrier layer, respectively, on the third high-k dielectric layer in all regions;
removing the barrier layer from the first region; and
forming a gate electrode over all regions.
2. The method according to claim 1 , wherein the semiconductor substrate is n-type, the method comprising:
forming a high-voltage threshold region in the first region;
forming a low-voltage threshold region in the second region; and
forming a super low-voltage threshold region in the third region.
3. The method according to claim 1 , wherein the semiconductor substrate is p-type, the method comprising:
forming a super low-voltage threshold region in the first region;
forming a low-voltage threshold region in the second region; and
forming a high-voltage threshold region in the third region.
4. The method according to claim 1 , comprising:
forming the third high-k dielectric layer based on a leakage current behavior of the second high-k dielectric layer.
5. The method according to claim 1 , comprising:
forming the second high-k dielectric layer based on a threshold-voltage shift target.
6. The method according to claim 1 , comprising:
forming the work-function composition layer by sandwiching a work-function metal layer between two layers of titanium nitride.
7. The method according to claim 1 , comprising:
forming the first high-k dielectric layer of hafnium-oxide to a thickness of 10 to 30 Å.
8. The method according to claim 1 , comprising:
forming the second high-k dielectric layer of lanthanum-oxide to a thickness of 0.1 to 20 Å.
9. The method according to claim 1 , wherein after the annealing process, the second high-k dielectric layer is driven into the first high-k dielectric layer with a higher concentration in proximity to the semiconductor substrate than near the gate electrode.
10. The method according to claim 1 , comprising:
determining an annealing temperature based on a concentration level of a metalloid in the second high-k dielectric layer.
11. A method comprising:
providing an interfacial layer along the entirety of and on an upper surface of a semiconductor substrate;
forming conformally a first high-k dielectric layer along the entirety of and on the interfacial layer while the interfacial layer exists along the entirety of the upper surface of the semiconductor substrate;
forming conformally a second high-k dielectric layer and a first cap layer, respectively, on the first high-k dielectric layer, wherein the second high-k dielectric layer is based on a threshold-voltage shift target;
removing the second high-k dielectric and first cap layers in first and second regions;
forming a second cap layer on the first high-k dielectric layer in the first and second regions and on the first cap layer in a third region;
performing an annealing process, wherein an annealing temperature is based on a concentration level of a metalloid in the second high-k dielectric layer;
removing the second cap layer from all regions and the first cap layer from the third region;
forming a third high-k dielectric layer over all regions, wherein the third high-k dielectric layer is based on a leakage current behavior of the second high-k dielectric layer;
forming conformally a work-function composition layer and a barrier layer, respectively, on the third high-k dielectric layer in all regions;
removing the barrier layer from the first region; and
forming a gate electrode over all regions.
12. The method according to claim 11 , wherein an n-type semiconductor substrate includes a high-voltage threshold region in the first region, a low-voltage threshold region in the second region, and a super low-voltage threshold region in the third region, and wherein a p-type semiconductor includes a super low-voltage threshold region in the first region, a low-voltage threshold region in the second region, and a high-voltage threshold region in the third region.