Pixel array with shared pixels in a single column and associated devices, systems, and methods
Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a floating diffusion region, a source a source follower transistor having a gate coupled to the floating diffusion region, a plurality of first pixels associated with a first color, and a plurality of second pixels associated with a second color different than the first color and arranged in a single column with the first pixels. The first and second pixels are configured to transfer charge to the floating diffusion region.
1. An imager, comprising:
a pixel array, including
a first floating diffusion region,
a second floating diffusion region,
a first source follower transistor having a gate coupled to the first floating diffusion region,
a second source follower transistor having a gate coupled to the second floating diffusion region,
a plurality of first pixels associated with a first color and configured to transfer charge to the first floating diffusion region,
a plurality of second pixels associated with a second color different than the first color, configured to transfer charge to the first floating diffusion region, and arranged in a single column with the first pixels
a plurality of third pixels associated with a third color different than the first and second colors, and
a plurality of fourth pixels associated with the first color, configured to transfer charge to the second floating diffusion region, and arranged in a single column with the third pixels; and
control circuitry operably coupled to the pixel array, wherein the control circuity is configured to successively read out onto a column line image signals corresponding to the charge transferred to the first floating diffusion region via each of the first and second pixels.
2. The imager of claim 1 , further comprising a ground line extending along the first column line.
3. The imager of claim 1 wherein the control circuitry is further configured to read out one of the first pixels at a time that is (1) after readout of one of the second pixels and (2) before readout of another one of the second pixels.
4. The imager of claim 1 , further comprising a reset transistor switchably coupling the first floating diffusion region to a reset line, wherein the control circuitry is further configured to reset the first floating diffusion region at a time that is (1) after readout of one of the first pixels and (2) before readout of one of the second pixels.
5. The pixel array of claim 1 wherein each of the first and second pixels includes a photosensor and a transfer transistor coupled to the photosensor, and wherein the control circuity is further configured to transfer charge generated by the photosensor to the first floating diffusion region.
6. The imager of claim 1 further comprising:
a sample and hold circuit; and
a column line transistor coupling the first source follower transistor to the sample and hold circuit.
7. The imager of claim 1 wherein the column line is a first column line and
the control circuity is further configured to successively read out onto a second column line image signals corresponding to the charge transferred to the floating diffusion region by each of the third and fourth pixels.
8. The imager of claim 7 further comprising a ground line between the single column of first and second pixels and the single column of third and fourth pixels.
9. The imager of claim 7 wherein the imager further comprises:
a first column line transistor coupled to the single column of first and second pixels; and
a second column line transistor coupled to the single column of third and fourth pixels.
10. A pixel array comprising:
a first floating diffusion region;
a second floating diffusion region;
a first source follower transistor having a gate coupled to the first floating diffusion region;
a second source follower transistor having a gate coupled to the second floating diffusion region;
a plurality of first pixels commonly coupled to the first floating diffusion region and associated with a first color;
a plurality of second pixels commonly coupled to the first floating diffusion region, associated with a second color different than the first color, and arranged in a single column with the first pixels;
a plurality of third pixels commonly coupled to the second floating diffusion region and associated with a third color different than the first and second colors; and
a plurality of fourth pixels commonly coupled to the second floating diffusion region, associated with the first color, and arranged in a single column with the third pixels.
11. The pixel array of claim 10 further comprising a column line transistor operably coupling the first source follower transistor to a sample and hold circuit.
12. The pixel array of claim 10 , further comprising a reset transistor switchably coupling the first floating diffusion region to a reset line over which the first floating diffusion region receives a reset signal.
13. The pixel array of claim 10 wherein each of the first and second pixels includes a photosensor and a transfer transistor configured to transfer photo-generated charge from the photosensor to the first floating diffusion region.
14. An imager, comprising:
a plurality of pixels including at least four pixels arranged in a first single column and alternatingly associated with a first color and a second color different than the first color;
a plurality of pixels including at least four pixels in a second single column and alternatingly associated with the first color and a third color different than the first and second colors;
a first floating diffusion region commonly coupled to the first single column of pixels;
a second floating diffusion region commonly coupled to the second single column of pixels;
a first source follower transistor;
a second source follower transistor; and
sample and hold circuitry operably coupled to (1) the first floating diffusion region via the first source follower transistor, and (2) the second floating diffusion region via the second source follower transistor.
15. The imager of claim 14 , further comprising control circuitry configured to read out each of the pixels of the first single column onto one column line and each of the pixels of the second single column onto another column line.
16. The imager of claim 14 , further comprising control circuitry configured to directly couple the first source follower transistor to a column line over which the sample and hold circuity receives an image signal from the first floating diffusion region.
17. The pixel array of claim 16 wherein the control circuity is further configured to switchably couple the first floating diffusion region to a reset line over which the first floating diffusion region receives a reset signal.