Data collection and compression in a solid state storage device
Methods for programming compressed data to a memory array, memory devices, and memory systems are disclosed. In one such method, memory pages or blocks that are partially programmed with valid data are found. The data is collected from these partially programmed pages or blocks and the data is compressed. The compressed data is then programmed back to different locations in the memory array of the memory device.
1. A method for data collection and compression in a memory device having a memory array, the method comprising:
determining whether memory pages of the memory array are only partially programmed with valid data by reading a status bit for each page, wherein the partially programmed memory pages have an unprogrammed area;
reading the valid data from the partially programmed memory pages in response to the respective status bit for each memory page;
compressing the read data in response to the respective status bit for each memory page; and
programming the compressed data back to the memory array.
2. The method of claim 1 wherein compressing the read data comprises using a GZIP algorithm to compress the read data.
3. The method of claim 2 and further including reading the compressed data from the memory array and using one of Lempel-Ziv (LZ) compression, DEFLATE, and GZIP to decompress the compressed data.
4. The method of claim 1 and further including programming an indication that the read data has been compressed.
5. The method of claim 1 and further including identifying a type of compression algorithm used in compressing the data.
6. The method of claim 1 and further including erasing the partially programmed memory pages after reading the data from the partially programmed memory pages.
7. The method of claim 1 and further including generating an indication that a first memory page is only partially programmed with valid data when data is moved from the first memory page.
8. The method of claim 1 and further including combining the compressed data with other compressed data prior to programming back to the memory array.
9. A memory device comprising:
a memory array organized in a plurality of memory pages and blocks; and
memory control circuitry, coupled to the memory array, for controlling operation of the memory device, the memory control circuitry configured to read a register comprising status bits indicating whether a respective memory page or memory block has only been partially programmed such that the respective memory page or memory block has an unprogrammed area, read data from the partially programmed pages or blocks in response to their respective status bit, compress the read data in response to their respective status bit, and program the compressed data to alternate locations of the memory array.
10. The memory device of claim 9 wherein the memory array is a NAND architecture flash memory array.
11. The memory device of claim 9 wherein each memory block is comprised of a plurality of memory pages.
12. The memory device of claim 9 wherein the memory control circuitry is further configured to generate an indication that the read data has been compressed and program the indication in memory.
13. The memory device of claim 9 wherein a circuit performs the compression.
14. The memory device of claim 9 wherein the compression is performed by a firmware routine.
15. The memory device of claim 9 wherein the memory control circuitry is further configured to compress all data that is written to the memory array.
16. A memory system comprising:
a controller for controlling operation of the memory system with memory signals;
a DRAM coupled to the controller; and
a solid state storage device, coupled to the controller and operating in response to the memory signals, the solid state storage device comprising:
an array of non-volatile memory cells organized in memory pages or blocks; and
memory control circuitry coupled to the array of memory cells and configured to find partially programmed memory blocks or pages that have unprogrammed areas by reading a status bit associated with each of the memory pages or blocks, read in response to each status bit valid data programmed in the partially programmed memory blocks or pages, compress the read data in response to each status bit, write the compressed data to the DRAM, identify the type of compression, and write both the compressed data from the DRAM and an indication of the type of compression to fill a memory block or page.
17. The memory system of claim 16 wherein the memory control circuitry is further configured to perform wear leveling by writing the compressed data to a plurality of physical addresses in response to a write operation to one logical address.
18. The memory system of claim 17 wherein the memory control circuitry is further configured to erase the partially programmed memory blocks.
19. The memory system of claim 16 wherein the memory control circuitry is further configured to read the indication of the type of compression and decompress the compressed data in response to the indication of the type of compression.