IP Library Granted Patent US 9,773,839
Granted Patent B2
US 9,773,839 · App. 14/790,535 · Granted Sep 26, 2017

Memory device having self-aligned cell structure

Inventors: Jun Liu (Boise, ID); Michael P. Violette (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/2409G11C11/5678H01L21/02532H01L21/31116H01L27/1021H01L27/2463H01L29/66136H01L45/04H01L45/06H01L45/141H01L45/1608G11C13/0004G11C2213/33G11C2213/72H01L45/1233H01L45/144
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Quick Facts
Patent No.
US 9,773,839
App. No.
14/790,535
Granted
Sep 26, 2017
Kind
B2
Abstract

Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.

Claims (70)

1. A method comprising:

forming device structures over a substrate, the device structures insulated from each other by a first insulation material, each of the device structures including a width and a length, the length extending in a first direction;

removing a portion of the device structures to form trenches extending in a second direction perpendicular to the first direction;

forming a second insulation material in the trenches;

removing a first material from the device structures to expose a second material of the device structures; and

forming diodes over the second material, wherein forming the device structures includes:

forming the second material over the substrate and forming the first material over the second material;

forming a first masking structure over the first material and the second material, the first masking structure including first openings, each of the first openings having a width and a length, the length extending in the first direction; and

removing a portion of the first material at the first openings and a portion of the second material at the first openings such that an unremoved portion of the first material and an unremoved portion of the second material form at least a part of the device structures.

2. The method of claim 1 , wherein removing the portion of the device structures to form the trenches includes:

forming a second masking structure over the device structures, the second masking structure including second openings, each of the second openings having a width and a length, the length extending in the second direction; and

removing the first material at the second openings to form the trenches.

3. The method of claim 1 , wherein forming diodes includes: forming an epitaxial silicon over the second material to form a first portion of each of the diodes; and inserting impurities into the epitaxial silicon to form a second portion of each of the diode.

4. The method of claim 1 , wherein the first material includes insulation material and the second material includes semiconductor material.

5. A method comprising:

forming device structures over a substrate, the device structures insulated from each other by a first insulation material, each of the device structures including a width and a length, the length extending in a first direction;

removing a portion of the device structures to form trenches extending in a second direction perpendicular to the first direction;

forming a second insulation material in the trenches;

removing a first material from the device structures to expose a second material of the device structures; and

forming diodes over the second material, wherein forming the device structures includes:

forming the second material over the substrate, forming a third material over the second material, and forming the first material over the third material;

forming a first masking structure over the first material, the first masking structure including first openings, each of the first openings having a width and a length, the length extending in the first direction; and

removing a portion of the first material at the first openings, a portion of the second material at the first openings, and a portion of the third material at the first openings such that an unremoved portion of the first material and an unremoved portion of the second material, and an unremoved portion of the third material form at least a part of the device structures.

6. The method of claim 5 , wherein removing the portion of the device structures to form the trenches includes:

forming a second masking structure over the device structures, the second masking structure including second openings, each of the second openings having a width and a length, the length extending in the second direction; and

removing the first material at the second openings to form the trenches and leaving at least a portion of the third material in the trenches.

7. The method of claim 6 , wherein the first material includes insulation material, the second material includes semiconductor material, and the third material includes conductive material.

8. The method of claim 7 , wherein the third material includes a combination of nickel and silicon.

9. The method of claim 1 further comprising: forming memory elements over the diodes.

10. The method of claim 9 , wherein forming memory elements includes depositing chalcogenide material over the diodes.

11. A method comprising:

forming device structures over a substrate, the device structures insulated from each other by an insulation material, each of the device structures including a width and a length, the length extending in a first direction;

forming a masking structure over the device structures, the masking structure including openings such that a first portion of a first material of the device structures are exposed at the openings and a second portion of the first material is underneath the masking structure, each of the openings having a width and a length, the length extending in a second direction perpendicular to the first direction;

removing a first portion of a first material at the openings from the device structures to expose a first portion of a second material of the device structures; and

forming diodes over the first portion of the second material, wherein forming the device structures includes:

forming the second material over the substrate and forming the first material over the second material;

forming an additional masking structure over the first material and the second material, the additional masking structure including first openings, each of the first openings having a width and a length, the length extending in the first direction; and

removing a second portion of the first material at the first openings and a portion of the second material at the first openings such that an unremoved portion of the first material and an unremoved portion of the second material form at least a part of the device structures.

12. A method comprising:

forming device structures over a substrate, the device structures insulated from each other by an insulation material, each of the device structures including a width and a length, the length extending in a first direction;

forming a masking structure over the device structures, the masking structure including openings such that a first portion of a first material of the device structures are exposed at the openings and a second portion of the first material is underneath the masking structure, each of the openings having a width and a length, the length extending in a second direction perpendicular to the first direction;

removing a first portion of a first material at the openings from the device structures to expose a first portion of a second material of the device structures; and

forming diodes over the first portion of the second material, wherein forming the device structures includes:

forming the second material over the substrate, forming the first material over the second material, and forming a third material over the second material;

forming an additional masking structure over the first material, the second material, and the third material, the additional masking structure including first openings, each of the first openings having a width and a length, the length extending in the second first direction; and

removing a second portion of the first material at the first openings, a portion of the second material at the first openings, and a portion of the third material at the first openings such that an unremoved portion of the first material, an unremoved portion of the second material, and an unremoved portion of the third material form at least a part of the device structures, wherein removing the portion of the first material at the openings also removes the portion of the third material to expose the second material.

13. The method of claim 12 , wherein the first material includes insulation material, the second material includes semiconductor material, and the third material includes conductive material.

14. A method comprising:

forming device structures over a substrate, the device structures insulated from each other by an insulation material, each of the device structures including a width and a length, the length extending in a first direction;

forming a masking structure over the device structures, the masking structure including openings such that a first portion of a first material of the device structures are exposed at the openings and a second portion of the first material is underneath the masking structure, each of the openings having a width and a length, the length extending in a second direction perpendicular to the first direction;

removing a first portion of a first material at the openings from the device structures and removing a portion of the insulation material to expose a first portion of a second material of the device structures; and

forming diodes over the first portion of the second material, wherein forming the diodes includes:

forming an epitaxial silicon over the second material to or a first portion of each of the diode; and

inserting impurities into the epitaxial silicon to form a second portion of each of the diode.

15. A method comprising:

forming device structures over a substrate, the device structures insulated from each other by an insulation material, each of the device structures including a width and a length, the length extending in a first direction;

forming a masking structure over the device structures, the masking structure including openings such that a first portion of a first material of the device structures are exposed at the openings and a second portion of the first material is underneath the masking structure, each of the openings having a width and a length, the length extending in a second direction perpendicular to the first direction;

removing a first portion of a first material at the openings from the device structures and removing a portion of the insulation material to expose a first portion of a second material of the device structures;

forming diodes over the first portion of the second material; and

forming memory elements such that each of the memory elements is coupled in series with one of the diodes between a first conductive line and a second conductive line.

16. A method comprising:

forming device structures over a substrate, the device structures insulated from each other by an insulation material, each of the device structures including a width and a length, the length extending in a first direction;

forming a masking structure over the device structures, the masking structure including openings such that a first portion of a first material of the device structures are exposed at the openings and a second portion of the first material is underneath the masking structure, each of the openings having a width and a length, the length extending in a second direction perpendicular to the first direction;

removing a first portion of a first material at the openings from the device structures to expose a first portion of a second material of the device structures;

forming diodes over the first portion of the second material;

removing the second portion of the first material to expose a second portion of the second material;

forming spacers in openings that are created after removal of the second portion of the first material; and

forming a third material over the diodes and the second portion of the second material.

17. The method of claim 16 , wherein the third material has a resistivity lower than a resistivity of the second material.

18. The method of claim 16 , wherein the third material includes a combination of cobalt and silicon.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (3)
Division 13959431 · Aug 5, 2013
Division 12367395 · Feb 6, 2009
Related Publication 20150303239A1 · Oct 22, 2015