Cell pillar structures and integrated flows
Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
1. A method comprising:
forming a source material;
forming an etch stop over the source material;
forming a memory stack over the etch stop, the memory stack comprising at least a first dielectric material, a second dielectric material, and a conductive material disposed between the first dielectric material and the second dielectric material;
forming an active semiconductor switching device over the memory stack;
forming a continuous pillar opening through the memory stack and the active semiconductor switching device to at least the etch stop;
etching a portion of the conductive material within the memory stack laterally away from the continuous pillar opening to form a recessed charge storage structure; and
filling the continuous pillar opening with a channel-fill material.
2. The method of claim 1 , further comprising forming the continuous pillar opening through the first dielectric material, the second dielectric material, and the conductive material forming a portion of the memory stack.
3. The method of claim 1 , further comprising:
forming an inter-polysilicon dielectric material on sidewalls of the continuous pillar opening and within the recessed storage structure; and
forming a charge storage material over the inter-polysilicon dielectric material.
4. The method of claim 3 , further comprising selecting the inter-polysilicon dielectric material to be a charge-blocking dielectric material.
5. The method of claim 3 , further comprising selecting the inter-polysilicon dielectric material to be a high-dielectric constant material.
6. The method of claim 3 , further comprising substantially removing the inter-polysilicon dielectric material and the charge storage material from the sidewalls and a bottom portion of the continuous pillar opening, wherein remaining portions of the inter-polysilicon dielectric material and the charge storage material remain substantially within the recessed charge storage structure.
7. The method of claim 6 , further comprising forming a tunneling material over at least the remaining portions of the inter-polysilicon dielectric material and the charge storage material.
8. The method of claim 1 , wherein the at least one active device is a conductive-bridging random-access memory cell.
9. The method of claim 1 , wherein an aspect ratio of an overall height of the continuous pillar opening to a width of the continuous pillar opening is about at least 35:1.
10. A method of forming an apparatus, the method comprising:
forming a source material;
forming an active semiconductor switching device;
forming an opening through a first dielectric material, a second dielectric material, and a conductive material disposed between the first dielectric material and the second dielectric material, the first dielectric material, the second dielectric material, and the conductive material being disposed between the source material and the active semiconductor switching device;
recessing the conductive material laterally from the opening to form a recessed control gate and to expose portions of the first dielectric material and the second dielectric material;
forming a charge storage element adjacent to the recessed control gate; and
forming a channel-fill material that is continuous from the source material to a level of the active semiconductor switching device.
11. The method of claim 10 , wherein the first dielectric material, the second dielectric material, and the conductive material forms at least a portion of a memory stack.