IP Library › Granted Patent US 9,793,380
Granted Patent B2
US 9,793,380 · App. 14/794,821 · Granted Oct 17, 2017

Semiconductor structure and fabrication method thereof

Inventors: Chih-Kai Hsu (Tainan, TW); Yu-Hsiang Hung (Tainan, TW); Ssu-I Fu (Kaohsiung, TW); Jyh-Shyang Jenq (Pingtung County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/66795H01L29/66545H01L29/785
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Quick Facts
Patent No.
US 9,793,380
App. No.
14/794,821
Granted
Oct 17, 2017
Kind
B2
Abstract

A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.

Claims (24)

1. A method for making a semiconductor device, comprising:

providing a substrate having a fin structure thereon;

forming a continuous dummy gate line on the substrate, wherein the dummy gate line strides across the fin structure;

forming a source/drain structure on the fin structure on either side of the dummy gate line;

forming an interlayer dielectric (ILD) on the dummy gate line and around the dummy gate line;

polishing the ILD to thereby reveal a top surface of the dummy gate line; and

after polishing the ILD, segmenting the dummy gate line into separated dummy gates.

2. The method for making a semiconductor device according to claim 1 , wherein the step of segmenting the dummy gate line into separated dummy gates further comprises:

forming a photoresist pattern on the ILD and on the top surface of the dummy gate line, wherein the photoresist pattern comprises an opening exposing a portion of the dummy gate line;

removing the exposed portion of the dummy gate line through the opening to thereby forming a cut slot; and

removing the photoresist pattern.

3. The method for making a semiconductor device according to claim 2 further comprising:

filling the cut slot with at least one dielectric layer.

4. The method for making a semiconductor device according to claim 3 , wherein the dielectric layer comprises a silicon oxide layer.

5. The method for making a semiconductor device according to claim 3 , wherein the step of filling the cut slot with at least one dielectric layer further comprises:

forming a liner layer within the cut slot.

6. The method for making a semiconductor device according to claim 5 , wherein the liner layer comprises a silicon nitride layer.

7. The method for making a semiconductor device according to claim 3 , wherein before filling the cut slot with at least one dielectric layer, the method further comprises:

filling the cut slot with a liner layer.

8. The method for making a semiconductor device according to claim 7 , wherein the liner layer comprises a silicon nitride layer.

9. The method for making a semiconductor device according to claim 1 further comprising:

removing the separated dummy gates to thereby form separated gate trenches; and

forming replacement gates into the separated gate trenches respectively.

10. The method for making a semiconductor device according to claim 1 , wherein the replacement gates comprise metal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2015
From: HSU, CHIH-KAI; HUNG, YU-HSIANG; FU, SSU-I; JENQ, JYH-SHYANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 036036/0470 →
Priority Claims (1)
TW 104120067 A · Jun 23, 2015 · national
Continuity (1)
Related Publication 20160379839A1 · Dec 29, 2016