Packaged devices with multiple planes of embedded electronic devices
A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.
1. A method for forming a packaged semiconductor structure, comprising:
placing first microelectronic device on a carrier, wherein a first major surface of the first microelectronic device is in contact with the carrier;
placing a substrate having a cavity over the first microelectronic device, wherein the substrate has a vertical portion surrounding the first microelectronic device and a horizontal portion over the first microelectronic device and a second microelectronic device attached to the horizontal portion of the substrate;
forming an encapsulant over the substrate wherein the encapsulant surrounds the first microelectronic device, the second microelectronic device, and the substrate, wherein the encapsulant contacts the first electronic device and the second electronic device, wherein the forming the encapsulant includes flowing encapsulant into the cavity through an opening in the substrate to contact the first microelectronic device;
removing the carrier, wherein removing the carrier exposes the first major surface of the first microelectronic device and the vertical portion of the substrate; and
forming an interconnect layer on the first major surface of the first microelectronic device, on the exposed vertical portion of the substrate and on a portion of the encapsulant.
2. The method of claim 1 , wherein prior to placing the substrate over the first microelectronic device, the method comprises attaching the second microelectronic device to the horizontal portion of the substrate.
3. The method of claim 1 , wherein prior to placing the substrate over the first microelectronic device, the method comprises:
attaching the second microelectronic device to a first interposer layer of the substrate; and
attaching a second interposer layer of the substrate to the first interposer layer, wherein the second interposer layer has an opening which surrounds the second microelectronic device, and wherein the first interposer layer comprises the horizontal portion of the substrate.
4. The method of claim 1 , further comprising:
prior to forming the encapsulant, attaching a plurality of interconnects to the substrate, wherein the substrate is between the plurality of interconnects and the interconnect layer, wherein forming the encapsulant is performed such that the encapsulant is also formed over the plurality of interconnects; and
grinding the semiconductor structure to expose a portion of each of the plurality of interconnects.
5. The method of claim 4 , further comprising:
attaching a third microelectronic device to the portion of each of the plurality of interconnects.
6. The method of claim 4 , further comprising:
forming a second plurality of interconnects on the interconnect layer, wherein the interconnect layer is between the second plurality of interconnects and the encapsulant.
7. The method of claim 1 wherein the forming the encapsulant includes flowing encapsulant into the cavity through an opening in the substrate to contact the second microelectronic device.