Method of manufacturing an electronic device including a semiconductor memory having a metal electrode and a metal compound layer surrounding sidewall of the metal electrode
A method of manufacturing an electronic device including a semiconductor memory is provided. The method may include forming a material layer for forming a variable resistance element over a substrate, forming a metal layer over the material layer, forming a mask pattern over the metal layer, forming a metal layer pattern by etching the metal layer using the mask pattern as an etch barrier, performing a surface treatment on the metal layer pattern, and etching the material layer using the metal layer pattern and the metal compound layer as an etch barrier to form a variable resistance element having an external side aligned with an external side of the metal compound layer. An external part of the metal layer pattern may be transformed into a metal compound layer. The metal compound layer may have a low etch rate as an etch barrier.
1. A method of manufacturing an electronic device comprising semiconductor memory, comprising:
forming a material layer for forming a variable resistance element over a substrate;
forming a metal layer over the material layer;
forming a mask pattern over the metal layer;
forming a metal layer pattern by etching the metal layer using the mask pattern as an etch barrier;
performing a surface treatment on the metal layer pattern so that an external part of the metal layer pattern is transformed into a metal compound layer having a low etch rate as an etch barrier; and
etching the material layer using the metal layer pattern and the metal compound layer as an etch barrier to form a variable resistance element having an external side aligned with an external side of the metal compound layer.
2. The method of claim 1 , wherein the forming of the material layer includes forming a sequentially stack structure including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer.
3. The method of claim 1 , wherein the forming of the material layer comprises forming a metal oxide layer.
4. The method of claim 1 , wherein the forming of the material layer comprises forming a phase change material layer.
5. The method of claim 1 , wherein the surface treatment is performed using plasma treatment or thermal treatment.
6. The method of claim 1 , wherein:
the surface treatment is performed to cause oxidation of the metal layer, and
the metal compound layer includes a metal oxide layer.
7. The method of claim 1 , wherein:
the surface treatment is performed in an atmosphere including nitrogen, and
the metal compound layer includes a metal nitride layer.
8. The method of claim 1 , wherein the forming of the variable resistance element is performed using a sputtering etching method.
9. The method of claim 8 , wherein the forming of the variable resistance element is performed using an ion beam etching method.
10. The method of claim 8 , wherein,
the surface treatment is performed in an atmosphere including oxygen, and
the metal compound layer includes a metal oxide layer.
11. The method of claim 1 , wherein the forming of the mask pattern comprises:
forming a first mask layer for gluing the metal layer and a second mask layer to be formed over the metal layer;
forming the second mask layer over the first mask layer; and
forming first and second mask patterns by selectively etching the first and the second mask layers.
12. The method of claim 11 , wherein the first mask layer comprises nitride.
13. The method of claim 11 , wherein the first mask layer has a non-stoichiometric composition.
14. The method of claim 11 , wherein the first mask layer has a smaller thickness than the second mask layer.
15. The method of claim 11 , wherein:
the first and the second mask patterns define a hole in which the mask pattern is to be formed.
16. The method of claim 11 , wherein the first and the second mask patterns cover a region where the variable resistance region is to be formed.
17. The method of claim 1 , wherein the metal compound layer vertically overlaps with the variable resistance element.
18. The method of claim 1 , wherein the metal layer pattern has a pillar shape, and the metal compound pattern has a cylindrical ring shape surrounding the metal layer pattern.
19. The method of claim 1 , wherein the metal compound layer completely surrounds a side of the metal layer pattern.
20. A method of manufacturing an electronic device comprising semiconductor memory, comprising:
forming a material layer for forming a variable resistance element over a substrate;
forming a metal layer over the material layer;
forming a mask pattern over the metal layer;
forming a preliminary metal layer pattern by etching the metal layer using the mask pattern as an etch barrier;
performing a surface treatment process to transform an external part of the preliminary metal layer pattern into a metal compound layer, wherein the preliminary metal layer pattern is formed to a metal layer pattern, wherein a width of the metal layer pattern is less than a width of the preliminary metal layer pattern; and
etching the material layer using the metal layer pattern and the metal compound layer as an etch barrier to form a variable resistance element having an external side aligned with an external side of the metal compound layer.
21. The method of claim 20 , wherein the metal compound layer is vertically overlapped with the variable resistance element.
22. The method of claim 20 , wherein the metal layer pattern has a pillar shape, and the metal compound pattern has a cylindrical ring shape.
23. The method of claim 20 , wherein the metal compound layer completely surrounds a side of the metal layer pattern.