Solid-state image pickup apparatus and electronic apparatus
A solid-state image pickup apparatus includes a pixel region in which a plurality of pixels each including a photoelectric conversion element are arranged, transfer wirings formed on the pixel region in parallel to each other with uniform opening widths, and different wirings formed in a wiring layer above the transfer wirings. At least a part of the different wirings is overlapped with the transfer wirings on a plan position. The transfer wirings and the different wirings form a light shielding structure in the pixel region.
1. An imaging device, comprising:
a first semiconductor chip unit including
a plurality of photoelectric conversion elements,
a first wiring layer having a first wiring, and
a second wiring layer having a second wiring coupled to a transfer gate associated with a respective photoelectric conversion element, and further having a third wiring that is a dummy wiring; and
a second semiconductor chip unit including a logic circuit, wherein
the first semiconductor chip unit is bonded to the second semiconductor chip unit,
the second wiring is adjacent the third wiring with a gap therebetween, such that the gap overlaps a portion of the respective photoelectric conversion element, in a plan view, and
the first wiring includes a first portion that overlaps a portion of the second wiring and a second portion that overlaps the gap, in the plan view.
2. The imaging device according to claim 1 , wherein the first semiconductor chip unit is electrically connected to the second semiconductor chip unit via a connection hole.
3. The imaging device according to claim 2 , wherein the connection hole includes a connected conductor.
4. The imaging device according to claim 2 , wherein the connection hole is covered with an insulating layer.
5. The imaging device according to claim 1 , wherein the first semiconductor chip unit is bonded to the second semiconductor chip unit with an adhesive layer.
6. The imaging device according to claim 1 , further comprising a stress correction film disposed between the first semiconductor chip unit and the second semiconductor chip unit.
7. The imaging device according to claim 1 , wherein the first semiconductor chip unit is bonded to the second semiconductor chip unit by plasma bonding.
8. The imaging device according to claim 1 , further comprising a color filter, an on-chip micro lens, and a flattening film.
9. The imaging device according to claim 1 , wherein
the first semiconductor chip unit includes a plurality of pixel transistors, and
the first wiring is electrically connected to at least one of the plurality of pixel transistors.
10. The imaging device according to claim 9 , wherein the plurality of pixel transistors includes:
a transfer transistor associated with the photoelectric conversion element and/or a floating diffusion,
a reset transistor disposed to allow charges to be selectively discharged from the floating diffusion to a circuit node, and
an amplification transistor coupled to the floating diffusion and configured to allow a signal corresponding to a potential of the floating diffusion to be output to a signal line.
11. The imaging device according to claim 10 , wherein the plurality of pixel transistors includes a selection transistor configured to selectively enable an operation of the amplification transistor.
12. The imaging device according to claim 11 , wherein the plurality of photoelectric conversion elements share the reset transistor, the amplification transistor, the selection transistor, and the floating diffusion.
13. The imaging device according to claim 10 , further comprising a column circuit connected to the signal line, wherein the column circuit is configured to perform a correlated double sampling and an analog-to-digital conversion.
14. The imaging device according to claim 1 , wherein the first, second, and third wirings are copper wirings.
15. An electronic apparatus, comprising:
an imaging device comprising
a first semiconductor chip unit including
a plurality of photoelectric conversion elements,
a first wiring layer having a first wiring, and
a second wiring layer having a second wiring coupled to a transfer gate associated with a respective photoelectric conversion element, and further having a third wiring that is a dummy wiring, and
a second semiconductor chip unit including a logic circuit; and
a signal processing circuit configured to process a pixel signal generated by the imaging device, wherein
the first semiconductor chip unit is bonded to the second semiconductor chip unit,
the second wiring is adjacent the third wiring with a gap therebetween, such that the gap overlaps a portion of the respective photoelectric conversion element, and
the first wiring includes a first portion that overlaps a portion of the second wiring and a second portion that overlaps the gap, in the plan view.
16. The electronic apparatus according to claim 15 , wherein the first semiconductor chip unit is electrically connected to the second semiconductor chip unit via a connection hole.
17. The electronic apparatus according to claim 16 , wherein the connection hole includes a connected conductor.
18. The electronic apparatus according to claim 17 , wherein the connection hole is covered with an insulating layer.
19. The electronic apparatus according to claim 16 , wherein the first semiconductor chip unit is bonded to the second semiconductor chip unit with an adhesive layer.
20. The electronic apparatus according to claim 16 , further comprising a stress correction film disposed between the first semiconductor chip unit and the second semiconductor chip unit.
21. The electronic apparatus according to claim 16 , wherein the first semiconductor chip unit is bonded to the second semiconductor chip unit by plasma bonding.
22. The electronic apparatus according to claim 16 , further comprising a color filter, an on-chip micro lens, and a flattening film.
23. The electronic apparatus according to claim 16 , wherein
the first semiconductor chip unit includes a plurality of pixel transistors, and
the first wiring is electrically connected to at least one of the plurality of pixel transistors.
24. The electronic apparatus according to claim 23 , wherein the plurality of pixel transistors includes:
a transfer transistor associated with the photoelectric conversion element and/or a floating diffusion,
a reset transistor disposed to allow charges to be selectively discharged from the floating diffusion to a circuit node, and
an amplification transistor coupled to the floating diffusion and configured to allow a signal corresponding to a potential of the floating diffusion to be output to a signal line.
25. The electronic apparatus according to claim 24 , wherein the plurality of pixel transistors includes a selection transistor configured to selectively enable an operation of the amplification transistor.
26. The electronic apparatus according to claim 25 , wherein the plurality of photoelectric conversion elements share the reset transistor, the amplification transistor, the selection transistor, and the floating diffusion.
27. The electronic apparatus according to claim 24 , further comprising a column circuit connected to the signal line, wherein the column circuit is configured to perform a correlated double sampling and an analog-to-digital conversion.
28. The electronic apparatus according to claim 16 , wherein the first, second, and third wirings are copper wirings.