IP Library Granted Patent US 9,809,898
Granted Patent B2
US 9,809,898 · App. 13/928,141 · Granted Nov 7, 2017

Electroplating and post-electrofill systems with integrated process edge imaging and metrology systems

Inventors: Daniel Mark Dinneen (Tigard, OR); James E. Duncan (Beaverton, OR)
Assignee: Lam Research Corporation
C25D17/001C25D21/10C25D21/12H01L21/67253H01L21/0209H01L21/02087H01L21/76877
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,809,898
App. No.
13/928,141
Granted
Nov 7, 2017
Kind
B2
Abstract

Disclosed herein are electroplating systems for forming a layer of metal on a wafer which include an electroplating module and a wafer edge imaging system. The electroplating module may include a cell for containing an anode and an electroplating solution during electroplating, and a wafer holder for holding the wafer in the electroplating solution and rotating the wafer during electroplating. The wafer edge imaging system may include a wafer holder for holding and rotating the wafer through different azimuthal orientations, a camera oriented for obtaining multiple azimuthally separated images of a process edge of the wafer while it is held and rotated (the process edge corresponding to the outer edge of the layer of metal formed on the wafer), and image analysis logic for determining an edge exclusion distance, wherein the edge exclusion distance is a distance between the wafer's edge and the process edge.

Claims (52)

1. An electroplating system for forming a layer of metal on a substantially circular wafer having a side edge, the system comprising:

an electroplating module comprising:

a cell for containing an anode and an electroplating solution during electroplating; and

a wafer holder for holding the wafer in the electroplating solution and rotating the wafer during electroplating;

an edge bevel removal module, the edge bevel removal module comprising:

a wafer holder for holding and rotating the wafer; and

a device for delivering etchant to an edge bevel region of the wafer while the wafer is held and rotated on the wafer holder of the edge bevel removal module to remove electroplated metal from the edge bevel region after electroplating in the electroplating module; and

a wafer edge imaging system comprising:

a wafer holder for holding and rotating the wafer through different azimuthal orientations;

a camera oriented for obtaining multiple azimuthally separated images of a process edge of the wafer while the wafer is held and rotated through different azimuthal orientations on the wafer holder of the imaging system, the process edge corresponding to the outer edge of the layer of metal formed on the wafer, wherein the camera is a color camera and each image generated by the color camera is represented as an array of pixels, each pixel comprising at least three color values; and

image analysis logic for determining an edge exclusion distance from the multiple azimuthally separated images, wherein the edge exclusion distance is a distance between the wafer's side edge and the process edge, wherein the image analysis logic further comprises EBR detection logic for determining from the multiple azimuthally separated images whether or not edge bevel removal (EBR) has been performed on the wafer by the edge bevel removal module; and

fault identification and reporting logic for reporting an error to an operator of the electroplating system when the image analysis logic determines that EBR has not been performed.

2. The electroplating system of claim 1 , further comprising fault identification and reporting logic for reporting an error to an operator of the electroplating system when the image analysis logic determines that an edge exclusion distance is outside a predetermined range.

3. The electroplating system of claim 1 , wherein the image analysis logic determines multiple azimuthally separated edge exclusion distances from the multiple azimuthally separated images, wherein each edge exclusion distance is a distance between the wafer's side edge and the process edge at a particular azimuthal angle.

4. The electroplating system of claim 3 , wherein the image analysis logic further comprises concentricity analysis logic for determining that the wafer's side edge and imaged process edge are concentric when a metric indicative of a statistical variation in the multiple edge exclusion distances over different azimuthal angles is within a predetermined threshold value and non-concentric when the metric exceeds the threshold value.

5. The electroplating system of claim 4 , wherein the metric is the standard deviation of the edge exclusion distances over different azimuthal angles.

6. The electroplating system of claim 4 , further comprising wafer centering adjustment logic for adjusting centering of one or more subsequently processed wafers within the electroplating module when a determination is made that a currently imaged wafer's side edge and process edge are non-concentric.

7. The electroplating system of claim 4 , further comprising fault identification and reporting logic for reporting an error to an operator of the electroplating system when the concentricity analysis logic determines that an imaged wafer's side edge and process edge are non-concentric.

8. The electroplating system of claim 1 , wherein the image analysis logic further comprises sharpness analysis logic for analyzing images of the process edge and determining a sharpness of the process edge in the images.

9. The electroplating system of claim 1 :

wherein the wafer edge imaging system is configured to operate in multiple imaging modes and to obtain multiple azimuthally separated images of the process edge using the multiple imaging modes; and

wherein the wafer edge imaging system further comprises an image optimization subsystem for determining an imaging mode which generates images of the process edge that are sharpest, and selecting the images generated using the imaging mode which generates images of the process edge that are sharpest for use by the image analysis logic to determine an edge exclusion distance.

10. The electroplating system of claim 9 , wherein the wafer edge imaging system includes an illumination subsystem having a light source with adjustable illumination intensity, and wherein the multiple imaging modes comprise distinct combinations of settings for illumination intensity and exposure times.

11. The electroplating system of claim 1 , wherein the wafer edge imaging system further comprises an illumination subsystem having a diffuse light source for illuminating the wafer's side edge with light comprising either diffuse low angle light or diffuse on-axis light relative to a horizontal plane of a surface of the wafer.

12. The electroplating system of claim 1 , wherein the image analysis logic further comprises logic for determining a taper width of the process edge from the multiple azimuthally separated images.

13. The electroplating system of claim 1 , the camera is a color camera.

14. The electroplating system of claim 13 , wherein each of the images generated by the color camera is represented as an array of pixels, each pixel comprising at least three color values.

15. The electroplating system of claim 14 , wherein in the multiple azimuthally separated images, the process edge is identified as a narrow region having the greatest color contrast between adjacent pixels.

16. The electroplating system of claim 15 :

wherein the image analysis logic further comprises logic for determining a taper width of the process edge from the multiple azimuthally separated images;

wherein the wafer edge imaging system is configured to operate in multiple imaging modes and to obtain multiple azimuthally separated images of the process edge using the multiple imaging modes; and

wherein the wafer edge imaging system further comprises an image optimization subsystem for determining an imaging mode which generates images of the process edge having the highest color contrast between pixels on either side of the process edge, and selecting the images generated using the imaging mode which generates images of the process edge having the highest color contrast between pixels on either side of the process edge for use by the image analysis logic to determine the taper width.

17. The electroplating system of claim 16 :

wherein the wafer edge imaging system further comprises an illumination subsystem having a diffuse light source for illuminating the wafer's side edge with diffuse low angle light relative to a horizontal plane of a surface of the wafer; and

wherein the wafer edge imaging system's multiple imaging modes comprises distinct combinations of settings for illumination intensity, and exposure times.

18. The electroplating system of claim 17 , wherein the multiple imaging modes further comprise distinct settings for color hue, saturation, and intensity.

19. The electroplating system of claim 1 , wherein the wafer holder of the wafer edge imaging system is the wafer holder of the edge bevel removal module.

20. The electroplating system of claim 1 , wherein the EBR detection logic determines whether or not EBR has been performed based on a difference between one or more of the three color values measured by the color camera at one or more pixels measured near the side edge of the wafer and one or more stored reference color values indicative of a color at a point on a wafer where a metal layer isn't present.

21. The electroplating system of claim 20 , wherein the metal is copper.

22. The electroplating system of claim 1 , wherein the process edge, of which the edge exclusion distance is determined in reference, is chosen for analysis by the image analysis logic based on the process edge's location within a predetermined radial range inward from the wafer's side edge.

23. A method of processing a substantially circular wafer comprising:

performing a processing operation on the wafer which forms a process edge of the wafer;

rotating the wafer through multiple azimuthal orientations;

obtaining multiple azimuthally separated color images of the process edge of the wafer while the wafer is rotated through the multiple azimuthal orientations, wherein each image generated by the color camera is represented as an array of pixels, each pixel comprising at least three color values;

identifying the process edge of the wafer in the multiple azimuthally separated images as a region having high contrast between adjacent pixels in the images;

determining an edge exclusion distance from the multiple azimuthally separated images by comparing the identified process edge with a side edge of the wafer appearing in the images;

determining from the multiple azimuthally separated images whether or not edge bevel removal (EBR) has been performed on the wafer by an edge bevel removal module, wherein the edge bevel module comprises a wafer holder for holding and rotating the wafer and a device for delivering etchant to an edge bevel region of the wafer while the wafer is held and rotated on the wafer holder of the edge bevel removal module to remove electroplated metal from the edge bevel region; and

reporting that the edge exclusion distance is outside a predetermined range.

24. The method of claim 23 , wherein the processing operation is electroplating.

25. The method of claim 23 , wherein the processing operation is edge bevel removal.

26. The method of claim 23 , wherein determining from the multiple azimuthally separated images whether or not edge bevel removal (EBR) has been performed on the wafer by an edge bevel removal module is based on based on a difference between one or more of the three color values measured by the color camera at one or more pixels measured near the side edge of the wafer and one or more stored reference color values indicative of a color at a point on a wafer where a metal layer isn't present.

27. The method of claim 26 , wherein the metal is copper.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2013
From: DINNEEN, DANIEL MARK; DUNCAN, JAMES E.
To: NOVELLUS SYSTEMS, INC.
Reel/Frame 030776/0907 →
Continuity (1)
Related Publication 20150001087A1 · Jan 1, 2015