Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof

1. A method for fabricating a semiconductor device, comprising:

etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches;

forming a protective layer with open parts to expose both sidewalls of each of the bodies;

forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and

forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines,

wherein the forming of the buried bit lines comprises:

forming a conductive layer on the protective layer with the open parts;

performing annealing to cause a reaction of the conductive layer with the bodies and silicidizing of the exposed portions of the bodies through the open parts;

forming a first dielectric layer on the conductive layer to gap-fill the trenches;

partially etching the first dielectric layer;

removing the conductive layer; and

forming a second dielectric layer on the first dielectric layer to gap-fill the trenches in such a manner that the air gaps are defined between the adjacent buried bit lines.

2. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer comprise oxide layers.

3. The method of claim 1 , wherein the forming of the protective layer with the open parts comprises:

forming a first protective layer on an entire surface of the etched semiconductor substrate including the bodies;

forming a second protective layer on the first protective layer;

forming a first sacrificial layer on the second protective layer to gap-fill the trenches;

partially etching the first sacrificial layer and the second protective layer;

forming a second sacrificial layer on the recessed second protective layer and the recessed first sacrificial layer to gap-fill the trenches;

partially etching the second sacrificial layer;

forming a third protective layer as spacers to cover the first protective layer exposed by the partially etched second protective layer;

forming preliminary open parts by selectively removing the partially etched first and second sacrificial layers; and

selectively removing the first protective layer exposed by the preliminary open parts.

4. The method of claim 3 , wherein the second protective layer and the third protective layer comprise nitride layers, and the first sacrificial layer and the second sacrificial layer comprise polysilicon layers.

5. The method of claim 3 , wherein the first protective layer comprises an oxide layer, and the second protective layer and the third protective layer comprise nitride layers.