Printed circuit board and package substrate
A printed circuit board includes an insulating substrate, a plurality of pads on a top surface of the insulating substrate, a protective layer formed on the insulating substrate and having an opening to expose top surfaces of the pads, a bump formed on at least one of the pads and protruding upward of a surface of the protective layer. The bump has a curved lateral side.
1. A printed circuit board comprising:
an insulating substrate;
a plurality of pads on a top surface of the insulating substrate;
a protective layer formed on the insulating substrate and having an opening to expose a top surface of the pads;
a bump formed on at least one of the pads and protruding upward of a surface of the protective layer; and
a seed layer between the at least one of the pads and the bump,
wherein the bump comprises:
a first bump portion filled in the opening of the protective layer and directly connected with a top surface of the one of the pads; and
a second bump portion on the first bump portion and protruding upward of the surface of the protective layer,
wherein the first bump portion is integrated with the second bump portion,
wherein an entire lateral side of the second bump portion has a curvature lateral surface,
wherein a width of the second bump portion is gradually decreased from an upper portion of the second bump portion to a point of inflection and gradually increased from the point of the inflection to a lower portion of the second bump portion,
wherein a width of the upper portion of the second bump portion is narrower than a width of the lower portion of the second bump portion, and
wherein the point of the inflection is higher than a central point of the curvature lateral surface of the second bump portion.
2. The printed circuit board of claim 1 , wherein the curvature lateral surface is a wet-etched lateral side surface.
3. The printed circuit board of claim 1 , further comprising an electronic device attached to at least one of remaining pads by a bonding ball formed on the at least one of the remaining pads,
wherein the electronic device is formed at an upper portion of the insulating substrate and exposed to an outside.
4. The printed circuit board of claim 3 , wherein the bump has a top surface higher than a top surface of the electronic device attached to the upper portion of the insulating substrate.
5. A package substrate comprising:
a lower substrate having at least one electronic device or at least one first chip attached thereto; and
an upper substrate having at least one second chip attached thereto and coupled to the lower substrate,
wherein the lower substrate comprises:
an insulating substrate;
a plurality of pads on a top surface of the insulating substrate;
a protective layer formed on the insulating substrate and having an opening to expose a top surface of the pads;
a plurality of bumps provided on the plurality of pads, protruding upward of a surface of the protective layer, and formed on a top surface thereof with a solder ball; and
a plurality of seed layers between the plurality of pads and the plurality of bumps,
wherein the upper substrate is supported by the plurality of bumps and attached to the lower substrate through the solder ball,
wherein each of the plurality of bumps comprises:
a first bump portion filled in the opening of the protective layer and directly connected with a top surface of the one of the pads; and
a second bump portion on the first bump portion and protruding upward of the surface of the protective layer,
wherein the first bump portion is integrated with the second bump portion,
wherein an entire lateral side of the second bump portion has a curvature lateral surface,
wherein a width of the second bump portion is gradually decreased from an upper portion of the second bump portion to a point of inflection and gradually increased from the point of the inflection to a lower portion of the second bump portion,
wherein a width of the upper portion of the second bump portion is narrower than a width of the lower portion of the second bump portion, and
wherein the point of the inflection is higher than a central point of the curvature lateral surface of the second bump portion.
6. The package substrate of claim 5 , wherein the at least one electronic device or the at least first chip is formed at an upper area of the insulating substrate between the bumps to be exposed to an outside, and has a top surface provided lower than the top surface of the bumps.