Semiconductor device and method of making
A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. A control gate structure includes a conductive layer that is spaced apart from the drain region by a first dimension in the lateral direction. A shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source and drain regions, wherein the second dimension is less than one-half of the first dimension.
1. A semiconductor device comprising:
a first region of a first conductivity type, the first region comprising a drain region;
a second region of a second conductivity type that is opposite the first conductivity type abutting the first region in a lateral direction to form an interface between the first conductivity type and the second conductivity type, the drain region spaced apart from the interface;
a source region of the first conductivity type abutting the second region in the lateral direction and a vertical direction;
a control gate structure comprising a conductive layer, the conductive layer being spaced apart from the drain region by a first dimension in the lateral direction; and
a shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source region and the drain region, the second dimension being equal to or less than one-half of the first dimension, and there are no other STI regions disposed between the source region and the drain region that abut the first region.
2. The semiconductor device of claim 1 , wherein the STI region is disposed between the conductive gate and the drain region.
3. The semiconductor device of claim 1 , wherein the interface is positioned in the lateral direction between first and second edges of the conductive layer.
4. The semiconductor device of claim 1 , wherein the source region is aligned to a first edge of the conductive layer that is furthest from the drain region in the lateral direction.
5. The semiconductor device of claim 1 further comprising an insulator layer starting at the control gate structure and ending at a silicide disposed at the drain region.
6. A semiconductor device comprising:
a first region of a first conductivity type, the first region comprising a drain region;
a second region of a second conductivity type that is opposite the first conductivity type abutting the first region in a lateral direction to form an interface between the first conductivity type and the second conductivity type, the drain region spaced apart from the interface;
a source region of the first conductivity type abutting the second region in the lateral direction and a vertical direction;
a control gate structure comprising a conductive layer, the conductive layer being spaced apart from the drain region by a first dimension in the lateral direction; and
a shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source region and the drain region, the second dimension being equal to or less than one-half of the first dimension, and there are no other STI regions disposed between the source region and the drain region that abut the first region, wherein the dimension of the STI region along the first lateral direction is less than one micro-meter.
7. A semiconductor device comprising:
a first region of a first conductivity type, the first region comprising a drain region;
a second region of a second conductivity type that is opposite the first conductivity type abutting the first region in a lateral direction to form an interface between the first conductivity type and the second conductivity type, the drain region spaced apart from the interface;
a source region of the first conductivity type abutting the second region in the lateral direction and a vertical direction;
a control gate structure comprising a conductive layer, the conductive layer being spaced apart from the drain region by a first dimension in the lateral direction; and
a shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source region and the drain region, the second dimension being equal to or less than one-half of the first dimension, and there are no other STI regions disposed between the source region and the drain region that abut the first region, wherein the second region includes a well region having a first dopant concentration that abuts the source region, and a third region that abuts the well region and the first region in the lateral direction and has a second dopant concentration that is less than the first dopant concentration, wherein the well region is spaced apart from the first region by the third region.
8. A semiconductor device comprising:
a first region of a first conductivity type, the first region comprising a drain region;
a second region of a second conductivity type that is opposite the first conductivity type abutting the first region in a lateral direction to form an interface between the first conductivity type and the second conductivity type, the drain region spaced apart from the interface;
a source region of the first conductivity type abutting the second region in the lateral direction and a vertical direction;
a control gate structure comprising a conductive layer, the conductive layer being spaced apart from the drain region by a first dimension in the lateral direction; and
a shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source region and the drain region, the second dimension being equal to or less than one-half of the first dimension, and there are no other STI regions disposed between the source region and the drain region that abut the first region, wherein the first region further comprises a third region, having a first dopant concentration, that abuts the drain region in the lateral direction.
9. The semiconductor device of claim 8 , wherein the third region extends further in the vertical direction than does the drain region.