Semiconductor package, semiconductor device using the same and manufacturing method thereof

1. A semiconductor package, comprising:

a substrate;

a first electronic component disposed on the substrate;

a first conductive layer;

a first pillar layer connecting the first conductive layer and the substrate; and

a first package body encapsulating the first conductive layer, the first pillar layer and the first electronic component;

wherein the first conductive layer is embedded in the first package body, and the first conductive layer includes a trace.

2. The semiconductor package as claimed in claim 1 , wherein the first conductive layer comprises a first pad exposed from the first package body, and the trace connects to the first pad.

3. The semiconductor package as claimed in claim 2 , wherein each of the first pad and the trace has a first lateral surface and a first upper surface, the first upper surface is exposed from the first package body, and the first lateral surface is encapsulated by the first package body.

4. The semiconductor package as claimed in claim 1 , wherein the first conductive layer comprises a plurality of the traces formed above the first electronic component.

5. The semiconductor package as claimed in claim 1 , wherein the first conductive layer has a thickness ranging between 10 micrometers and 20 micrometers.

6. The semiconductor package as claimed in claim 1 , wherein the first package body is molding compound.

7. The semiconductor package as claimed in claim 1 , wherein the first conductive layer has a first upper surface, the first package body has a second upper surface, and the first upper surface is aligned with the second upper surface.

8. A semiconductor package, comprising:

a substrate;

a first electronic component disposed on the substrate;

a first conductive layer;

a first pillar layer connecting the first conductive layer and the substrate;

a first package body encapsulating the first conductive layer, the first pillar layer and the first electronic component;

a second conductive layer;

a second pillar layer connecting the first conductive layer and the second conductive layer; and

a second package body encapsulating the second conductive layer and the second pillar layer;

wherein the first conductive layer is embedded in the first package body.

9. The semiconductor package as claimed in claim 8 , wherein the first conductive layer comprises a first pad exposed from the first package body and a trace connecting to the first pad.

10. The semiconductor package as claimed in claim 9 , wherein each of the first pad and the trace has a first lateral surface and a first upper surface, the first upper surface is exposed from the first package body, and the first lateral surface is encapsulated by the first package body.

11. The semiconductor package as claimed in claim 8 , wherein the first conductive layer comprises a plurality of the traces formed above the first electronic component, and the second conductive layer comprises a plurality of second pads formed above the traces.

12. The semiconductor package as claimed in claim 8 , wherein the first conductive layer has a first upper surface, the first package body has a second upper surface, and the first upper surface is aligned with the second upper surface.

13. The semiconductor package as claimed in claim 8 , wherein the second conductive layer comprises a second pad exposed from the second package body.

14. The semiconductor package as claimed in claim 13 , wherein the second pad has a second lateral surface and a third upper surface, the third upper surface is exposed from the second package body, and the second lateral surface is encapsulated by the second package body.

15. The semiconductor package as claimed in claim 8 , wherein the first conductive layer has a thickness ranging between 10 micrometer and 20 micrometer.

16. The semiconductor package as claimed in claim 8 , wherein the first package body is a molding compound.

17. The semiconductor package as claimed in claim 8 , wherein the second package body is a lamination layer.

18. The semiconductor package as claimed in claim 8 , wherein the second conductive layer has a third upper surface, the second package body has a fourth upper surface, and the third upper surface is aligned with the fourth upper surface.

19. A semiconductor device, comprising:

a semiconductor package as claimed in claim 1 ; and

a second electronic component disposed on the first conductive layer of the semiconductor package.

20. A semiconductor device, comprising:

a semiconductor package as claimed in claim 8 ; and

a second electronic component disposed on the second conductive layer of the semiconductor package.

21. A manufacturing method of a semiconductor package, comprising:

providing a carrier;

forming a first conductive layer on the carrier;

forming a first pillar layer on the first conductive layer;

disposing a first electronic component on a substrate;

connecting the first pillar layer to the substrate;

forming a first package body to encapsulate the first electronic component, the first conductive layer and the first pillar layer; and

removing the carrier.

22. The manufacturing method as claimed in claim 21 , further comprises:

forming a second conductive layer on the carrier;

forming a second package body to encapsulate the second conductive layer;

forming a second pillar layer passing through the second package body, wherein the second pillar layer is electrically connected to the second conductive layer;

wherein in the step of forming the first conductive layer on the carrier, the first conductive layer is formed on the carrier through the second pillar layer.