IP Library Granted Patent US 9,892,679
Granted Patent B2
US 9,892,679 · App. 15/262,174 · Granted Feb 13, 2018

Display device

Inventor: Hajime Kimura (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G09G3/3225G09G3/3233G09G3/3266H01L27/124H01L27/1255H01L27/3262H01L27/3265G09G3/3275G09G2300/0809G09G2300/0814G09G2300/0819G09G2300/0842G09G2300/0852G09G2300/0861G09G2300/0876G09G2310/027G09G2310/0251G09G2320/0204G09G2320/0233G09G2320/0252G09G2320/043G09G2320/045G09G2380/02H01L27/3244H01L27/3295H01L51/524H01L51/5237H01L51/5253H01L51/5259
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Quick Facts
Patent No.
US 9,892,679
App. No.
15/262,174
Granted
Feb 13, 2018
Kind
B2
Abstract

A voltage equal to the threshold value of a TFT ( 106 ) is held in capacitor unit ( 109 ). When a video signal is inputted from a source signal line, the voltage held in the capacitor unit is added thereto and a resultant signal is applied to a gate electrode of the TFT ( 106 ). Even when a threshold value is varied for each pixel, each threshold value is held in the capacitor unit ( 109 ) for each pixel. Thus, the influence of a variation in threshold value can be eliminated. Further, holding of the threshold value is conducted by only the capacitor unit ( 109 ) and a charge does not move at writing of a video signal so that a voltage between both electrodes is not changed. Thus, it is not influenced by a variation in capacitance value.

Claims (107)

1. A display device comprising:

a pixel comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a first capacitor; and

a light-emitting element,

wherein the pixel does not comprise any transistor other than the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a current supply line,

wherein a first electrode of the first capacitor is electrically connected to a gate of the first transistor,

wherein a second electrode of the first capacitor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a source signal line,

wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the light-emitting element,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the first electrode of the first capacitor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the second electrode of the first capacitor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,

wherein a gate of the second transistor is electrically connected to a first gate signal line, and

wherein a gate of the fourth transistor is electrically connected to a second gate signal line.

2. The display device according to claim 1 , further comprising a second capacitor,

wherein a first electrode of the second capacitor is electrically connected to the second electrode of the first capacitor, and

wherein a second electrode of the second capacitor is electrically connected to the current supply line.

3. A display device comprising:

a first gate signal line driver circuit configured to output a first pulse to a first gate signal line in accordance with a start pulse, the first gate signal line driver circuit being configured to output a second pulse to a second gate signal line in accordance with the start pulse;

a second gate signal line driver circuit configured to output a third pulse to a third gate signal line; and

a pixel between the first gate signal line driver circuit and the second gate signal line driver circuit, the pixel comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a first capacitor; and

a light-emitting element,

wherein the first gate signal line is electrically connected to the pixel,

wherein the second gate signal line is electrically connected to the pixel,

wherein the third gate signal line is electrically connected to the pixel,

wherein one of a source and a drain of the first transistor is electrically connected to a current supply line,

wherein a first electrode of the first capacitor is electrically connected to a gate of the first transistor,

wherein a second electrode of the first capacitor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a source signal line,

wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the light-emitting element,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the first electrode of the first capacitor,

wherein one of a source and a drain of the sixth transistor is electrically connected to the second electrode of the first capacitor, and

wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor.

4. The display device according to claim 3 , further comprising a second capacitor,

wherein a first electrode of the second capacitor is electrically connected to the second electrode of the first capacitor, and

wherein a second electrode of the second capacitor is electrically connected to the current supply line.

5. A display device comprising:

a first gate signal line driver circuit electrically connected to a first gate signal line and a second gate signal line;

a second gate signal line driver circuit electrically connected to a third gate signal line; and

a pixel between the first gate signal line driver circuit and the second gate signal line driver circuit, the pixel comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a first capacitor; and

a light-emitting element,

wherein the first gate signal line is electrically connected to the pixel,

wherein the second gate signal line is electrically connected to the pixel,

wherein the third gate signal line is electrically connected to the pixel,

wherein one of a source and a drain of the first transistor is directly connected to a current supply line,

wherein a first electrode of the first capacitor is directly connected to a gate of the first transistor,

wherein a second electrode of the first capacitor is directly connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is directly connected to a source signal line,

wherein one of a source and a drain of the third transistor is directly connected to the gate of the first transistor,

wherein the other of the source and the drain of the third transistor is directly connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the fourth transistor is directly connected to the light-emitting element,

wherein the other of the source and the drain of the fourth transistor is directly connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to the first electrode of the first capacitor,

wherein one of a source and a drain of the sixth transistor is directly connected to the second electrode of the first capacitor, and

wherein the other of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the sixth transistor.

6. The display device according to claim 5 , further comprising a second capacitor,

wherein a first electrode of the second capacitor is electrically connected to the second electrode of the first capacitor, and

wherein a second electrode of the second capacitor is electrically connected to the current supply line.

7. The display device according to claim 1 ,

wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor.

8. The display device according to claim 1 ,

wherein a gate of the third transistor is electrically connected to a third gate signal line.

9. The display device according to claim 1 ,

wherein a gate of the sixth transistor is electrically connected to a fourth gate signal line.

10. The display device according to claim 3 ,

wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor.

11. The display device according to claim 3 ,

wherein the first gate signal line is electrically connected to a gate of the second transistor.

12. The display device according to claim 3 ,

wherein the second gate signal line is electrically connected to a gate of the third transistor.

13. The display device according to claim 3 ,

wherein the third gate signal line is electrically connected to a gate of the fourth transistor.

14. The display device according to claim 5 ,

wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor.

15. The display device according to claim 5 ,

wherein the first gate signal line is electrically connected to a gate of the second transistor.

16. The display device according to claim 5 ,

wherein the second gate signal line is electrically connected to a gate of the third transistor.

17. The display device according to claim 5 ,

wherein the third gate signal line is electrically connected to a gate of the fourth transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2016
From: KIMURA, HAJIME
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 040272/0627 →
Priority Claims (1)
JP 2001-326397 · Oct 24, 2001 · national
Continuity (8)
Continuation 14797246 · Jul 13, 2015
Continuation 14527921 · Oct 30, 2014
Continuation 14184757 · Feb 20, 2014
Continuation 13767038 · Feb 14, 2013
Continuation 13267261 · Oct 6, 2011
Continuation 12110379 · Apr 28, 2008
Continuation 10279000 · Oct 24, 2002
Related Publication 20170053594A1 · Feb 23, 2017