IP Library › Granted Patent US 9,905,520
Granted Patent B2
US 9,905,520 · App. 13/162,297 · Granted Feb 27, 2018

Solder ball protection structure with thick polymer layer

Inventors: Chen-Hua Yu (Hsin-Chu, TW); Lawrence Chiang Sheu (Hsin-Chu, TW); Hao-Yi Tsai (Hsin-Chu, TW); Chien-Hsiun Lee (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L24/05H01L23/3114H01L24/11H01L24/13H01L24/16H01L2224/0401H01L2224/05012H01L2224/05147H01L2224/05155H01L2224/05556H01L2224/05558H01L2224/05569H01L2224/05571H01L2224/05572H01L2224/05647H01L2224/05666H01L2224/1146H01L2224/11849H01L2224/131H01L2224/16225H01L2224/16227H01L2924/00014H01L2924/014H01L2924/01023H01L2924/01029H01L2924/12042H01L2924/3512
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Quick Facts
Patent No.
US 9,905,520
App. No.
13/162,297
Granted
Feb 27, 2018
Kind
B2
Abstract

An integrated circuit structure includes a substrate and a metal pad over the substrate. A post-passivation interconnect (PPI) line is connected to the metal pad, wherein the PPI line includes at least a portion over the metal pad. A PPI pad is connected to the PPI line. A polymer layer is over the PPI line and the PPI pad, wherein the polymer layer has a thickness greater than about 30 μm. An under-bump metallurgy (UBM) extends into an opening in the polymer layer and electrically connected to the PPI pad.

Claims (13)

1. An integrated circuit structure comprising:

a substrate;

a low-k dielectric layer over the substrate;

a copper-containing pad in the low-k dielectric layer;

a first metal pad and a second metal pad over the substrate and neighboring each other, wherein a top surface of the copper-containing pad is in physical contact with a bottom surface of the first metal pad;

a passivation layer over the low-k dielectric layer, wherein the passivation layer comprises a first portion overlapping edge portions of the first metal pad, and a second portion level with the first metal pad, wherein a portion of the passivation layer between the first metal pad and the second metal pad has a first top surface, and portions of the passivation layer directly overlying the first metal pad and the second metal pad have second top surfaces higher than the first top surface;

a first polymer layer over the passivation layer;

a post-passivation interconnect (PPI) line connected to the first metal pad, wherein the PPI line comprises a via portion extending into the first polymer layer to contact the first metal pad, and wherein the first portion of the passivation layer is spaced apart from the via portion of the PPI line by the first polymer layer;

a PPI pad connected to the PPI line, wherein the PPI pad is an extending portion of the PPI line;

a second polymer layer over the PPI line and the PPI pad; and

a first and a second under-bump metallurgy (UBM) extending into openings in the second polymer layer, wherein the first UBM is electrically connected to the PPI pad, and wherein the second polymer layer comprises a top surface continuously extending from directly under a first overhang portion of the first UBM to directly under a second overhang portion of the second UBM.

2. The integrated circuit structure of claim 1 , wherein a thickness of the second polymer layer is greater than about 30 μm.

3. The integrated circuit structure of claim 1 , wherein the top surface of the second polymer layer is substantially flat, and wherein portions of the top surface of the second polymer layer that are directly under the first and the second overhang portions are substantially level with a portion of the top surface of the second polymer layer not directly under the first and the second overhang portions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2011
From: YU, CHEN-HUA; SHEU, LAWRENCE CHIANG; TSAI, HAO-YI; LEE, CHIEN-HSIUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 026861/0188 →
Continuity (1)
Related Publication 20120319251A1 · Dec 20, 2012