IP Library Granted Patent US 9,911,840
Granted Patent B2
US 9,911,840 · App. 14/635,988 · Granted Mar 6, 2018

Self aligned trench MOSFET with integrated diode

Inventors: Sik Lui (Sunnyvale, CA); Anup Bhalla (Santa Clara, CA)
Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
H01L29/7397H01L21/7688H01L21/76877H01L27/0635H01L27/10823H01L27/10876H01L29/0834H01L29/407H01L29/4236H01L29/66348H01L29/66666H01L29/66704H01L29/66719H01L29/66727H01L29/66734H01L29/7395H01L29/7804H01L29/7805H01L29/7806H01L29/7811H01L29/7813H01L29/8613H01L29/872H01L29/1095H01L29/41766H01L29/456H01L29/47
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Quick Facts
Patent No.
US 9,911,840
App. No.
14/635,988
Granted
Mar 6, 2018
Kind
B2
Abstract

A transistor device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.

Claims (13)

1. A self-aligned transistor device, comprising

a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in gate trenches in the substrate;

one or more body regions formed in a top portion of the substrate proximate each gate trench; one or more source regions formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench;

one or more thick insulator portions formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions, wherein the one or more thick insulator portions are in a configuration where they are thicker at edges thereof than at central portions over the gate electrodes, and wherein the thick insulator portions include portions of a sidewall dielectric spacer formed as a trench mask for the gate trenches, and wherein the sidewall dielectric spacer is only included in the thick insulator portions that are thicker at the edges, and wherein the sidewall dielectric spacer is made of a different material than an insulator material that forms part of the thick insulator portions; and

one or more metal layers formed on top of the substrate over the thick insulator portions, wherein the metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions, wherein an integrated diode is formed under said self-aligned contact, wherein the integrated diode is a fast recovery diode.

2. The device of claim 1 wherein the metal, body region and substrate are configured such that the integrated diode is a Schottky diode.

3. The device of claim 1 wherein the metal, body region and substrate are configured such that the integrated diode is a low injection efficiency P-N junction diode.

4. The device of claim 1 wherein the gate trenches further comprise a shield electrode located under the gate electrodes.

5. The device of claim 1 , further comprising a collector region characterized by a doping of a polarity type opposite that of the doped substrate, wherein the collector region is formed at a side of the substrate opposite a side where the gate trenches are formed, whereby the device is an insulated gate bipolar transistor (IGBT).

6. The device of claim 1 , wherein the semiconductor substrate is made from an N-type semiconductor material.

7. The device of claim 1 , wherein the semiconductor substrate is made from a P-type semiconductor material.

8. The device of claim 1 , wherein the source and body regions are configured such that portions of the substrate where there are no source or body regions extend up to a surface of the substrate.

9. The device of claim 8 , wherein the one or more metal layers are formed on the surface of the substrate over the thick insulator portions, the portions of the one or more body regions, portions of the one or more source regions, and the portions of the substrate where there are no source or body regions that extend up to a surface of the substrate, wherein the metal forms a self-aligned contact to the portions of the one or more body regions, the portions of the one or more source regions, and the portions of the substrate where there are no source or body regions that extend up to a surface of the substrate through the spaces between the thick insulator portions, wherein an integrated diode is formed under said self-aligned contact, wherein the integrated diode is the fast recovery diode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2015
From: LUI, SIK; BHALLA, ANUP
To: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
Reel/Frame 035337/0349 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2015
From: LUI, SIK; BHALLA, ANUP
To: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
Reel/Frame 035075/0954 →
Continuity (3)
Division 14060974 · Oct 23, 2013
Division 12968179 · Dec 14, 2010
Related Publication 20150171201A1 · Jun 18, 2015