IP Library Granted Patent US 9,928,331
Granted Patent B2
US 9,928,331 · App. 14/561,280 · Granted Mar 27, 2018

Method and control device for circuit layout migration

Inventors: Vladimir Pavlovich Rozenfeld (Andreevka, RU); Robert L. Maziasz (Austin, TX); Mikhail Anatolievich Sotnikov (Moscow, RU)
Assignee: NXP USA, Inc.
G06F17/5072G06F17/5063
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Quick Facts
Patent No.
US 9,928,331
App. No.
14/561,280
Granted
Mar 27, 2018
Kind
B2
Abstract

A method for circuit layout migration comprises creating a list of layout components in a source layout; determining a plurality of first groups of layout components being regularly aligned horizontally or vertically; determining first subsets of layout components which each belong to at least two of a respective set of determined first groups; determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components; determining symmetry axes for pairs of second groups; building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups and distance constraints for preserving a regularity pattern within each of the second groups and symmetry constraints for the determined symmetry axes for pairs of second groups; and performing constraint-graph-based compaction of the source layout.

Claims (49)

1. A method for manufacturing a set of masks based on circuit layout migration:

wherein the circuit layout migration includes,

creating a list of layout components in a source layout, wherein the list of layout components in a source layout includes conducting wires;

determining a plurality of first groups of layout components being regularly aligned horizontally or vertically;

determining first subsets of layout components which each belong to at least two of a respective set of determined first groups of layout components;

determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components;

determining symmetry axes for pairs of second groups in the source layout;

building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups, distance constraints for keeping regularity patterns within each of the second groups, and symmetry constraints for the determined symmetry axes for pairs of second groups; and

performing constraint graph based compaction of the source layout using the built constraint graph; and

wherein the manufacturing includes,

manufacturing the set of masks based on the constraint graph based compaction of the source layout.

2. The method of claim 1 , wherein determining the first subsets of layout components comprises:

creating a bipartite graph with the first groups of layout components as graph vertices and common membership of at least one layout component between two first groups as graph edges; and

associating the layout components of graph vertices being interconnected by graph edges with the respective first subsets of layout components.

3. The method of claim 2 , wherein the bipartite graph comprises two disjoint sets of vertices, a first of the disjoint sets consisting of first groups of layout components being regularly aligned horizontally and a second of the disjoint sets consisting of first groups of layout components being regularly aligned vertically.

4. The method of claim 3 , wherein, if two or more pairs of second groups comprise the same symmetry axis, the respective symmetry axes are merged.

5. The method of claim 2 , wherein, if two or more pairs of second groups comprise the same symmetry axis, the respective symmetry axes are merged.

6. The method of claim 1 , wherein, if two or more pairs of second groups comprise the same symmetry axis, the respective symmetry axes are merged.

7. The method of claim 6 , wherein a first constraint-graph-based compaction of the source layout is performed using the alignment constraints for the alignment of layout components within each of the second groups, and

wherein a second constraint-graph-based compaction of the source layout is using the distance constraints for preserving regularity pattern within each of the second groups, and wherein a third constraint-graph-based compaction is using the symmetry constraints for the determined symmetry axes for pairs of second groups.

8. The method of claim 7 , wherein building the constraint graph of the layout components of the source layout uses distance constraints between adjacent layout components, and wherein the constraint graph of the layout components of the source layout is fixed for possible constraint conflicts by taking into account symmetry constraints.

9. The method of claim 1 , wherein a first constraint-graph-based compaction of the source layout is performed using the alignment constraints for the alignment of layout components within each of the second groups, and

wherein a second constraint-graph-based compaction of the source layout is using the distance constraints for preserving regularity pattern within each of the second groups, and wherein a third constraint-graph-based compaction is using the symmetry constraints for the determined symmetry axes for pairs of second groups.

10. The method of claim 1 , wherein building the constraint graph of the layout components of the source layout uses distance constraints between adjacent layout components, and wherein the constraint graph of the layout components of the source layout is fixed for possible constraint conflicts by taking into account symmetry constraints.

11. A control device for manufacturing a set of masks based on circuit layout migration:

wherein the circuit layout migration includes,

a list generator engine configured to create a list of layout components in a source layout, wherein the list of layout components in a source layout includes conducting wires;

a component group generator engine configured to determine a plurality of first groups of layout components being regularly aligned horizontally or vertically, to determine first subsets of layout components which each belong to at least two of a respective set of determined first groups of layout components, and to determine a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components;

a graph generator engine configured to build a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups, distance constraints between adjacent layout components within each of the second groups and symmetry constraints for determined symmetry axes for pairs of second groups; and

a layout compaction engine configured to perform constraint-graph-based compaction of the source layout using the built constraint graph; and

wherein the manufacturing includes,

manufacturing the set of masks based on the constraint-graph-based compaction of the source layout.

12. The control device of claim 11 , wherein the component group generator engine is further configured to create a bipartite graph with the first groups of layout components as graph vertices and common membership of at least one layout component between two first groups as graph edges, and to associate the layout components of graph vertices being interconnected by graph edges with the respective first subsets of layout components.

13. The control device of claim 12 , wherein, if two or more pairs of second groups comprise the same symmetry axis, the component group generator engine is configured to merge the respective symmetry axes.

14. The control device of claim 11 , wherein, if two or more pairs of second groups comprise the same symmetry axis, the component group generator engine is configured to merge the respective symmetry axes.

15. The control device of claim 14 , wherein the layout compaction engine is configured to perform a first constraint-graph-based compaction of the source layout using the alignment constraints for the alignment of layout components within each of the second groups, and a second constraint-graph-based compaction of the source layout using distance constraints between adjacent layout components within each of the second groups, and a third constraint-graph-based compaction of the source layout using only the symmetry constraints for the determined symmetry axes for pairs of second groups.

16. The control device of claim 15 , wherein the graph generator engine is further configured to use distance constraints between adjacent layout components in building the constraint graph of the layout components.

17. The control device of claim 11 , wherein the layout compaction engine is configured to perform a first constraint-graph-based compaction of the source layout using the alignment constraints for the alignment of layout components within each of the second groups, and a second constraint-graph-based compaction of the source layout using distance constraints between adjacent layout components within each of the second groups, and a third constraint-graph-based compaction of the source layout using only the symmetry constraints for the determined symmetry axes for pairs of second groups.

18. The control device of claim 11 , wherein the graph generator engine is further configured to use distance constraints between adjacent layout components in building the constraint graph of the layout components.

19. An integrated circuit including structures based on circuit layout migration:

wherein the circuit layout migration includes,

creating a list of layout components in a source layout, wherein the list of layout components in a source layout includes conducting wires;

determining a plurality of first groups of layout components being regularly aligned horizontally or vertically;

determining first subsets of layout components which each belong to at least two of a respective set of determined first groups of layout components;

determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components;

determining symmetry axes for pairs of second groups in the source layout;

building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups, distance constraints for keeping regularity patterns within each of the second groups, and symmetry constraints for the determined symmetry axes for pairs of second groups; and

performing constraint graph based compaction of the source layout using the built constraint graph; and

wherein the integrated circuit structures are based on the constraint graph based compaction of the source layout.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2014
From: ROZENFELD, VLADIMIR PAVLOVICH; MAZIASZ, ROBERT L.; SOTNIKOV, MIKHAIL ANATOLIEVICH
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034535/0942 →
Priority Claims (1)
RU 2014122499 · Jun 4, 2014 · national
Continuity (1)
Related Publication 20150356224A1 · Dec 10, 2015